PEB2245N-V12 Infineon Technologies, PEB2245N-V12 Datasheet - Page 22

• Manufacturer Part Number: PEB2245N-V12
• Description: IC SWITCHING/CONFER MULTI 44PLCC
• Manufacturer: Infineon Technologies
• Series: MUSAC™r

Specifications of PEB2245N-V12

• Function: Multipoint Switching and Conferencing
• Interface: PCM
• Voltage - Supply: 5V
• Current - Supply: 12mA
• Power (watts): 100mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Includes: Clock Shift, Space Switch Mode, Time and Space Switch, Tristate Function
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Number Of Circuits: -
• Other names: PEB2245N-V12; PEB2245N-V12IN

Table 2
Possible Input Modes
Input Modes
16
8
4
2
4
The PEB 2245 runs with either a 4096- or a 8192-kHz device clock as selected with CFR:CPS. Data
rates and clock frequencies may be combined freely. However, processing 8192-kbit/s data, an
8192-kHz clock must be supplied.
The preparation of the input data according to the selected input mode is made in the input buffer.
It converts the serial data of a time-slot to parallel form.
In standard configuration time-slot 0 begins with the rising edge of the SP pulse as shown in upper
half of figure 11 denoted CSR:(0000XXXX).
As can be seen there the beginning of a input time-slot is defined such, that the input lines have
settled to a stable value, when the datum is actually sampled.
4096- and 8192-kbit/s data is sampled in the middle of the bit period at the falling edge of the
respective data clock. 2048-kbit/s data is sampled after 3/4 of the according bit period, i.e. with the
rising edge of the 4
considered bit period.
In the primary access configuration a different timing scheme may apply to the odd (physical) input
lines. They are affected by the content of the clock shift register (CSR), which can be programmed
via the P interface (see paragraph 2.2).
The clock shift register holds the information, how the frame structure is shifted in the primary
access configuration. Its content defaults to 00
whenever the standard configuration is selected.
Semiconductor Group
8192
4096
+
+
th
8192-kHz clock cycle or the falling edge of the 2
2048
4096
8192
8
8
2048
2048
kbit/s
kbit/s
kbit/s
kbit/s
kbit/s
22
H
after power up and is also set to this value,
Type
Single mode
Single mode
Single mode
Mixed mode
Mixed mode
nd
4096-kHz clock cycle of the
PEB 2245