PEB 20532 F V1.3 Infineon Technologies, PEB 20532 F V1.3 Datasheet - Page 32

• Manufacturer Part Number: PEB 20532 F V1.3
• Description: IC CTRLR 2CH SERIAL TQFP-100
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20532FV1.3X; SP000007512

Table 1
Pin No.
Table 2
Pin No.
Data Sheet
P-TQFP-
100-3
19
P-TQFP-
100-3
84
86
Microprocessor Bus Interface
External DMA Interface
Symbol In (I)
RESET I
Symbol In (I)
DRTA
DRRA
Out (O)
Out (O)
O
O
Function
Reset
With this active low signal the on-chip registers
and state machines are forced to reset state.
During Reset all pins are in a high impedance
state.
Function
DMA Request Transmitter Channel A
The transmitter on a this channel requests a DMA
transfer by activating the DRTA line. The request
remains active as long as the Transmit FIFO
requires data transfers. The amount of data bytes
to be transferred from the system memory to the
serial channel (= Byte Count) must be written first
to the XBCL,
data (n x 32 bytes + rest ; n=0,1,…) are
transferred till the Byte Count is reached. DRTA is
deactivated with the beginning of the last write
cycle.
DMA Request Receiver Channel A
The receiver on this serial channel requests a
DMA transfer by activating the DRRA line. The
request remains active as long as the Receive
FIFO requires data transfers, thus always blocks
of data are transferred. DRRA is deactivated
immediately following the falling edge of the last
read cycle.
32
XBCH
registers. Always blocks of
Pin Descriptions
PEB 20532
PEF 20532
2000-09-14