PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 59
PEF 2054 N V2.1
Manufacturer Part Number
PEF 2054 N V2.1
Description
IC INTERFACE CTRLR PCM LCC-44
Manufacturer
Infineon Technologies
Series
EPICr
Datasheet
1.PEF_2054_N_V2.1.pdf
(269 pages)
Specifications of PEF 2054 N V2.1
Function
PCM Interface Controller
Interface
ISDN, PCM
Number Of Circuits
1
Voltage - Supply
5V
Current - Supply
9.5mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-LCC
Includes
Board Controller, Channel Switching
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEF2054NV2.1XT
PEF2054NV21XK
SP000057916
SP000075438
PEF2054NV21XK
SP000057916
SP000075438
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Access in multiplexed P-interface mode:
CDS2..0
CUS3..0
4.2.2.5 Configurable Interface Bit Shift Register (CBSR)
Access in demultiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
0
CFI Downstream bit Shift 2..0.
From the zero offset bit position (CBSR = 20
and upstream) can be shifted by up to 6 bits to the left (within the time slot
number TSN programmed in CTAR) and by up to 2 bits to the right (within
the previous time slot TSN – 1) by programming the CBSR:CDS2..0 bits:
CBSR:CDS2..0
000
001
010
011
100
101
110
111
The bit shift programmed to CBSR:CDS2..0 affects both the upstream and
downstream frame position in the same way.
CFI Upstream bit Shift 3..0.
These bits shift the upstream CFI frame relative to the downstream frame by
up to 15 bits. For CUS3..0 = 0000, the upstream frame is aligned with the
downstream frame (no bit shift).
CDS2
H
CDS1
CDS0
Time Slot No.
TSN – 1
TSN – 1
TSN
TSN
TSN
TSN
TSN
TSN
59
CUS3
read/write
read/write
Detailed Register Description
H
CUS2
) the CFI frame (downstream
Bit No.
1
0
7
6
5
4
3
2
address: A
OMDR:RBS = 1
address: 34
CUS1
PEB 2055
PEF 2055
H
bit 0
H
CUS0
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