SC16C850LIBS,151 NXP Semiconductors, SC16C850LIBS,151 Datasheet - Page 30

• Manufacturer Part Number: SC16C850LIBS,151
• Description: IC UART SINGLE W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16C850LIBS,151

• Number Of Channels: 1, UART
• Package / Case: 32-VFQFN Exposed Pad
• Features: Programmable
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 1.95 V
• Supply Voltage (min): 1.65 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4206; 935283086151; SC16C850LIBS-S

NXP Semiconductors
SC16C850L
Product data sheet
7.8 Modem Status Register (MSR)
This register shares the same address as EFCR register. This is a read-only register and
it provides the current state of the control interface signals from the modem, or other
peripheral device to which the SC16C850L is connected. Four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
When write, the data will be written to EFCR register.
Table 21.
[1]
Bit
7
6
5
4
2
1
0
3
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Modem Status Register bits description
All information provided in this document is subject to legal disclaimers.
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
CD. During normal operation, this bit is the complement of the CD input.
DSR. During normal operation, this bit is the complement of the DSR input.
CTS. During normal operation, this bit is the complement of the CTS input.
Description
Reading this bit in the loopback mode produces the state of MCR[3] (OP2).
RI. During normal operation, this bit is the complement of the RI input.
Reading this bit in the loopback mode produces the state of MCR[2] (OP1).
During the loopback mode, this bit is equivalent to MCR[0] (DTR).
During the loopback mode, this bit is equivalent to MCR[1] (RTS).
CD
RI
DSR
CTS
Rev. 5 — 1 February 2011
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C850L has changed state since the last
time it was read. A modem Status Interrupt will be generated.
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C850L has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C850L has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C850L has changed state since the
last time it was read. A modem Status Interrupt will be generated.
[1]
[1]
[1]
[1]
SC16C850L
© NXP B.V. 2011. All rights reserved.
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