SC16IS752IPW,112 NXP Semiconductors, SC16IS752IPW,112 Datasheet - Page 22

• Manufacturer Part Number: SC16IS752IPW,112
• Description: IC UART DUAL 12C/SPI 28TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16IS752IPW,112

• Number Of Channels: 2, DUART
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Features: Low Current
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4016-5; 935279292112; SC16IS752IPW; SC16IS752IPW

NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
8.1 Receive Holding Register (RHR)
8.2 Transmit Holding Register (THR)
8.3 Interrupt Enable Register (IER)
The receiver section consists of the Receive Holding Register (RHR) and the Receive
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, location zero of the FIFO is used to store the byte.
Characters are lost if overflow occurs.
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Modem Status, Xoff received, or CTS/RTS change of
state from LOW to HIGH. The IRQ output signal is activated in response to interrupt
generation.
Table 11.
Bit
7
6
5
4
3
2
Symbol
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
IER[2]
Interrupt Enable Register bits description
Table 11
[1]
[1]
[1]
[1]
Description
CTS interrupt enable.
RTS interrupt enable.
Xoff interrupt.
Sleep mode.
Modem Status interrupt.
Remark: See IOControl register bit 1 or bit 2 (in
of how to program the pins as modem pins.
Receive Line Status interrupt.
shows Interrupt Enable Register bit settings.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
logic 0 = disable the Modem Status Register interrupt (normal default
condition)
logic 1 = enable the Modem Status Register interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
Dual UART with I
Rev. 07 — 19 May 2008
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Section 7.6 “Sleep mode”
Table
29) for the description
© NXP B.V. 2008. All rights reserved.
for details.
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