SC16C650BIBS,151 NXP Semiconductors, SC16C650BIBS,151 Datasheet - Page 20

• Manufacturer Part Number: SC16C650BIBS,151
• Description: IC UART SINGLE W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDAr

Specifications of SC16C650BIBS,151

• Number Of Channels: 1, UART
• Package / Case: 32-VFQFN Exposed Pad
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 3 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3275; 935276404151; SC16C650BIBS-S

NXP Semiconductors
SC16C650B_4
Product data sheet
Table 10.
Table 11.
Table 12.
Bit
3
(cont.)
2
1
0
FCR[7]
0
0
1
1
FCR[5]
0
0
1
1
Symbol
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
RCVR trigger levels
TX FIFO trigger levels
FCR[6]
0
1
0
1
FCR[4]
0
1
0
1
Rev. 04 — 14 September 2009
Description
Transmit operation in mode ‘1’: When the SC16C650B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0
when FIFO has 1 empty space.
Receive operation in mode ‘1’: When the SC16C650B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a
logic 1 when other FCR bits are written to, or they will not be
programmed.
RX FIFO trigger level (bytes)
8
16
24
28
TX FIFO trigger level (bytes)
16
8
24
30
UART with 32-byte FIFOs and IrDA encoder/decoder
…continued
SC16C650B
© NXP B.V. 2009. All rights reserved.
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