SC68C752BIBS,151 NXP Semiconductors, SC68C752BIBS,151 Datasheet - Page 10
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SC68C752BIBS,151
Manufacturer Part Number
SC68C752BIBS,151
Description
IC UART DUAL W/FIFO 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC68C752BIBS151.pdf
(48 pages)
Specifications of SC68C752BIBS,151
Number Of Channels
2, DUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3299
935280969151
SC68C752BIBS-S
935280969151
SC68C752BIBS-S
NXP Semiconductors
SC68C752B_4
Product data sheet
6.3.1 Receive flow control
6.3.2 Transmit flow control
There are two other enhanced features relating to software flow control:
When software flow control operation is enabled, the SC68C752B will compare incoming
data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be
received sequentially). When the correct Xoff character are received, transmission is
halted after completing transmission of the current character. Xoff detection also sets
IIR[4] (if enabled via IER[5]) and causes IRQ to go HIGH.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level
programmed in TCR[3:0].
Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level
programmed in TCR[7:4].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7
characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xon2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)
It is assumed that software flow control and hardware flow control will never be enabled
simultaneously.
•
•
Xon Any function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an Xon Any character, which could cause an Xon2 character to be
written to the RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.
Figure 7
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
shows an example of software flow control.
SC68C752B
© NXP B.V. 2010. All rights reserved.
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