CY8C5368LTI-026 Cypress Semiconductor Corp, CY8C5368LTI-026 Datasheet - Page 40

• Manufacturer Part Number: CY8C5368LTI-026
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5368LTI-026

• Lead Free Status / Rohs Status: Compliant

Figure 7-13. Digital System Interconnect
Interrupt and DMA routing is very flexible in the CY8C53
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design.
(Interrupt/DMA Multiplexer).
Figure 7-14. Interrupt and DMA Processing in the IDMUX
Document Number: 001-66237 Rev. *A
Fixed Function DRQs
Counters
Timer
Fixed Function IRQs
Clocks
Global
Figure 7-14
CAN
IO Port
Pins
UDB Array
I2C
Interrupt and DMA Processing in IDMUX
Digital System Routing I/F
Digital System Routing I/F
shows the structure of the IDMUX
UDB ARRAY
Del-Sig
IRQs
DRQs
Controller
Interrupt
SC/CT
Blocks
Detect
Detect
Edge
Edge
Controller
DMA
DACs
0
1
2
0
1
2
3
PRELIMINARY
IO Port
Pins
Comparators
DMA termout (IRQs)
Controller
Controller
Clocks
Interrupt
Global
DMA
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the system clock (see
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-15. I/O Pin Synchronization Routing
Figure 7-16. I/O Pin Output Connectivity
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
DO
DI
PIN 0
PSoC
DO
8 IO Data Output Connections from the
UDB Array Digital System Interface
PIN1
DO
®
5: CY8C53 Family Datasheet
PIN2
DO
Figure
PIN3
DO
6-1). Normally all inputs from pins
Port i
PIN4
DO
PIN5
DO
Page 40 of 106
PIN6
DO
PIN7
DO
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