CY8C5366LTI-053 Cypress Semiconductor Corp, CY8C5366LTI-053 Datasheet - Page 4

• Manufacturer Part Number: CY8C5366LTI-053
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5366LTI-053

• Lead Free Status / Rohs Status: Compliant

In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C53 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the
Peripherals”
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1% error over
temperature and voltage. The configurable analog subsystem
includes:
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C53 family also offers a SAR ADC. Featuring 12-bit
conversions at up to 1 M samples per second, it also offers low
nonlinearity and offset errors and SNR better than 70 dB. It is
well suited for a variety of higher speed analog applications.
Two high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADC and DACs, the analog subsystem
provides multiple:
See the
sheet for more details.
Document Number: 001-66237 Rev. *A
Analog muxes
Comparators
Analog mixers
Voltage references
Analog-to-Digital Converters (ADC)
Digital-to-Analog Converters (DACs)
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
“Analog Subsystem”
section on page 32 of this data sheet. For
section on page 32 of this data sheet.
2
C slave, master, and multimaster;
section on page 45 of this data
PRELIMINARY
“Example
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 67 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s
byte-writeable EEPROM. It provides up to 256 KB of on-chip
flash. The CPU can reprogram individual blocks of flash,
enabling boot loaders. A powerful and flexible protection model
secures the user's sensitive information, allowing selective
memory block locking for read and write protection. Two KB of
byte-writable EEPROM is available on-chip to store application
data.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the V
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow V
to be set independently of V
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with Full-Speed USB the USB physical interface is
also provided (USBIO). When not using USB these pins may
also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the
data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 67 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power internal low speed oscillator (ILO) for the sleep
and watchdog timers. A 32.768 KHz external watch crystal is
also supported for use in real time clock (RTC) applications. The
clocks, together with programmable clock dividers, provide the
flexibility to integrate most timing requirements.
PSoC
nonvolatile
“I/O System and Routing”
®
2
C bus where the PSoC may not be powered when
5: CY8C53 Family Datasheet
subsystem
DDIO
when used as outputs. When
consists
section on page 26 of this
DDIO
pins. Every GPIO
of
Page 4 of 106
flash
and
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