CY8C5366LTI-053 Cypress Semiconductor Corp, CY8C5366LTI-053 Datasheet - Page 44

• Manufacturer Part Number: CY8C5366LTI-053
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5366LTI-053

• Lead Free Status / Rohs Status: Compliant

7.8 I
The I
designed to interface the PSoC device with a two wire I
communication bus. The bus is compliant with Philips ‘The I
Specification’ version 2.1. Additional I
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I
and generation of framing bits. I
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I
DSI routing and allows direct connections to any GPIO or SIO
pins.
Document Number: 001-66237 Rev. *A
SDA
SCL
2
2
C peripheral provides a synchronous two wire interface
C
Condition
START
2
C specific support is provided for status detection
ADDRESS
1 - 7
2
C operates as a slave, a master,
R/W
8
2
C interfaces through the
2
C interfaces can be
Figure 7-22. I
ACK
9
PRELIMINARY
2
C serial
2
1 - 7
C Complete Transfer Timing
2
DATA
C
I
Data transfers follow the format shown in
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address
another slave without first generating a STOP condition. Various
combinations of read/write formats are then possible within such
a transfer.
2
C features include:
8
Slave and Master, Transmitter, and Receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
PSoC
ACK
9
®
5: CY8C53 Family Datasheet
1 - 7
DATA
8
Figure
ACK
9
Page 44 of 106
7-22. After the
Condition
STOP
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