CY8C5468LTI-037 Cypress Semiconductor Corp, CY8C5468LTI-037 Datasheet - Page 9

• Manufacturer Part Number: CY8C5468LTI-037
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5468LTI-037

• Lead Free Status / Rohs Status: Compliant

3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3
Low resistance output pin for high current DACs (IDAC).
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out
High current output of uncommitted opamp
Extref0, Extref1
External reference input to the analog system.
OpAmp0–, OpAmp1–, OpAmp2–, OpAmp3–
Inverting input to uncommitted opamp.
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+
Noninverting input to uncommitted opamp.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
32.768 KHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4 to 25 MHz crystal oscillator pin. If a crystal is not used then Xi
must be shorted to ground and Xo must be left floating.
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
SWDCK
Serial Wire Debug Clock programming and debug port connection.
SWDIO
Serial Wire Debug Input and Output programming and debug
port connection.
SWV
Single Wire Viewer output.
USBIO, D+
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from Vddd instead of from a
Vdddio. Pins are Do Not Use (DNU) on devices without USB.
Document Number: 001-66238 Rev. *A
Note
6. GPIOs with opamp outputs are not recommended for use with CapSense.
[6]
.
Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
Plane
Vssd
[6]
.
PRELIMINARY
Vddd
Vssd
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from Vddd instead of from a
Vdddio. Pins are DNU on devices without USB.
V
Power sense connection to boost pump.
V
Battery supply to boost pump.
V
Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to Vssa. Regulator output not for
external use.
V
Output of digital core regulator and input to digital core. The two
Vccd pins must be shorted together, with the trace between them
as short as possible, and a 1 µF capacitor to Vssd; see
System
V
Supply for all analog peripherals and analog core regulator.
V
other supply pins must be less than or equal to V
V
Supply for all digital peripherals and digital core regulator. V
must be less than or equal to V
V
Ground for all analog peripherals.
V
Ground connection for boost pump.
V
Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3
Supply for I/O pins. Each V
voltage (2.7 V to 5.5 V), and must be less than or equal to Vdda.
XRES. External reset pin. Active low with internal pull-up.]
BOOST
BAT
CCA
CCD
DDA
DDA
DDD
SSA
SSB
SSD
PSoC
Vssa
must be the highest voltage present on the device. All
Vdda
on page 21. Regulator output not for external use.
®
5: CY8C54 Family Datasheet
Plane
Vssa
DDIO
DDA
must be tied to a valid operating
.
Page 9 of 105
DDA
Power
.
DDD
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