SC16C2550BIBS,157 NXP Semiconductors, SC16C2550BIBS,157 Datasheet - Page 12
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SC16C2550BIBS,157
Manufacturer Part Number
SC16C2550BIBS,157
Description
IC DUART SOT617-1
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C2550BIA44518.pdf
(43 pages)
Specifications of SC16C2550BIBS,157
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
3.5 V ~ 4.5 V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935280309157
SC16C2550BIBS
SC16C2550BIBS
SC16C2550BIBS
SC16C2550BIBS
NXP Semiconductors
SC16C2550B_5
Product data sheet
6.5 Programmable baud rate generator
The SC16C2550B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC16C2550B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable baud rate generator is capable of
operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is necessary
to use full rail swing on the clock input. The SC16C2550B can be configured for internal or
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins.
Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates (see
The generator divides the input 16 clock by any divisor from 1 to (2
SC16C2550B divides the basic external clock by 16. The basic 16 clock provides table
rates to support standard and custom applications using the same system design. The
rate table is configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in
selectable baud rate table available when using a 1.8432 MHz external clock input.
Fig 6.
Crystal oscillator connection
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 05 — 12 January 2009
XTAL1
1.8432 MHz
C1
22 pF
X1
XTAL2
C2
33 pF
XTAL1
1.8432 MHz
C1
22 pF
Table
X1
XTAL2
7).
002aaa870
SC16C2550B
1.5 k
C2
47 pF
16
Table 7
© NXP B.V. 2009. All rights reserved.
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