SC68C752BIBS,128 NXP Semiconductors, SC68C752BIBS,128 Datasheet - Page 23
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SC68C752BIBS,128
Manufacturer Part Number
SC68C752BIBS,128
Description
IC UART DUAL 32HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC68C752BIBS128.pdf
(48 pages)
Specifications of SC68C752BIBS,128
Number Of Channels
2, DUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935280969128
SC68C752BIBS-F
SC68C752BIBS-F
SC68C752BIBS-F
SC68C752BIBS-F
NXP Semiconductors
SC68C752B_4
Product data sheet
7.4 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR.
shows the Line Control Register bit settings.
Table 13.
Bit
7
6
5
4
3
2
1:0
Symbol
LCR[7]
LCR[6]
LCR[5]
LCR[4]
LCR[3]
LCR[2]
LCR[1:0]
Line Control Register bits description
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Description
Divisor latch enable.
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TXn output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
Parity type select.
Parity enable.
Number of stop bits. Specifies the number of stop bits.
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no break condition (normal default condition)
logic 1 = forces the transmitter output (TXn) to a logic 0 to alert the
communication terminal to a line break condition
logic 0 = parity is not forced (normal default condition)
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the
transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the
transmit and receive data.
logic 0 = odd parity is generated (if LCR[3] = 1).
logic 1 = even parity is generated (if LCR[3] = 1).
logic 0 = no parity (normal default condition).
logic 1 = a parity bit is generated during transmission and the receiver
checks for received parity.
0 = 1 stop bit (word length = 5, 6, 7, 8)
1 = 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
Rev. 04 — 20 January 2010
SC68C752B
© NXP B.V. 2010. All rights reserved.
Table 13
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