SC68C752BIBS,157 NXP Semiconductors, SC68C752BIBS,157 Datasheet - Page 19
![IC UART DUAL 32HVQFN](/photos/6/51/65170/568-32-hvqfn_sml.jpg)
SC68C752BIBS,157
Manufacturer Part Number
SC68C752BIBS,157
Description
IC UART DUAL 32HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC68C752BIBS128.pdf
(48 pages)
Specifications of SC68C752BIBS,157
Number Of Channels
2, DUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935280969157
SC68C752BIBS
SC68C752BIBS
SC68C752BIBS
SC68C752BIBS
NXP Semiconductors
7. Register descriptions
SC68C752B_4
Product data sheet
Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table
Table 10.
[1]
[2]
[3]
[4]
[5]
[6]
A2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
Fig 13. Crystal oscillator connections
MCR[7] can only be modified when EFR[4] is set.
Accessed by a combination of address pins and register bits.
Accessible only when LCR[7] is logic 1.
Accessible only when LCR is set to 1011 1111 (BFh).
Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables.
Accessible only when CS = 0, MCR[2] = 1, and loopback is disabled (MCR[4] = 0).
10.
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
Register map - read/write properties
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
Read mode
Receive Holding Register (RHR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
Line Control Register (LCR)
Modem Control Register (MCR)
Line Status Register (LSR)
Modem Status Register (MSR)
ScratchPad Register (SPR)
Divisor Latch LSB (DLL)
Divisor Latch MSB (DLM)
Enhanced Feature Register (EFR)
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmission Control Register (TCR)
Trigger Level Register (TLR)
FIFO ready register
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
XTAL1
1.8432 MHz
C1
22 pF
[2][4]
[2][4]
[2][4]
[2][4]
X1
XTAL2
[2][6]
C2
33 pF
[2][3]
[2][3]
[2][5]
[1]
[2][4]
XTAL1
[2][5]
1.8432 MHz
C1
22 pF
Write mode
Transmit Holding Register (THR)
Interrupt Enable Register
FIFO Control Register (FCR)
Line Control Register
Modem Control Register
ScratchPad Register
divisor latch LSB
divisor latch MSB
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmission Control Register
Trigger Level Register
X1
XTAL2
002aaa870
1.5 kΩ
C2
47 pF
SC68C752B
[2][4]
[2][4]
[2][4]
[2][4]
© NXP B.V. 2010. All rights reserved.
[2][3]
[2][3]
[2][5]
[1]
[2][4]
19 of 48
[2][5]