SC28L92A1BS,557 NXP Semiconductors, SC28L92A1BS,557 Datasheet - Page 38
![IC UART DUAL W/FIFO 44PQFP](/photos/6/92/69297/48-hvqfn_sot778-3_pkg_sml.jpg)
SC28L92A1BS,557
Manufacturer Part Number
SC28L92A1BS,557
Description
IC UART DUAL W/FIFO 44PQFP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L92A1B557.pdf
(73 pages)
Specifications of SC28L92A1BS,557
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935281063557
SC28L92A1BS
SC28L92A1BS
SC28L92A1BS
SC28L92A1BS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L92A1BS,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC28L92_7
Product data sheet
Table 42.
Bit
4
3
2
1
0
Symbol
-
TxEMTA
TxRDYA
FFULLA
RxRDYA
SRA - Status register channel A (address 0x1) bit description
Description
Channel A overrun error.
This bit, when set, indicates that one or more characters in the received data
stream have been lost. It is set upon receipt of a new character when the FIFO
is full and a character is already in the receive shift register waiting for an empty
FIFO position. When this occurs, the character in the receive shift register (and
its break detect, parity error and framing error status, if any) is lost.
This bit is cleared by a reset error status command.
Channel A transmitter empty.
This bit will be set when the transmitter under runs, i.e., both the TxEMT and
TxRDY bits are set. This bit and TxRDY are set when the transmitter is first
enabled and at any time it is re-enabled after either (a) reset, or (b) the
transmitter has assumed the disabled state. It is always set after transmission
of the last stop bit of a character if no character is in the Tx Holding Register
(TxFIFOA) awaiting transmission.
It is reset when the Tx Holding Register (TxFIFOA) is loaded by the CPU, a
pending transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the under run condition.
Channel A transmitter ready.
This bit, when set, indicates that the transmit FIFO is not full and ready to be
loaded with another character. This bit is cleared when the transmit FIFO is
loaded by the CPU and there are (after this load) no more empty locations in
the FIFO. It is set when a character is transferred to the transmit shift register.
TxRDYA is reset when the transmitter is disabled and is set when the
transmitter is first enabled. Characters loaded to the Tx FIFO while this bit is
logic 0 will be lost. This bit has different meaning from ISR[0].
Channel A FIFO full.
This bit is set when a character is transferred from the receive shift register to
the receive FIFO and the transfer causes the FIFO to become full, i.e., all eight
(or 16) FIFO positions are occupied. It is reset when the CPU reads the receive
FIFO. If a character is waiting in the receive shift register because the FIFO is
full, FFULLA will not be reset when the CPU reads the receive FIFO. This bit
has different meaning from ISR1 when MR1[6] is programmed to a logic 1
Channel A receiver ready.
This bit indicates that a character has been received and is waiting in the FIFO
to be read by the CPU. It is set when the character is transferred from the
receive shift register to the FIFO and reset when the CPU reads the receive
FIFO, only if (after this read) there are no more characters in the FIFO - the Rx
FIFO becomes empty.
0 = no
1 = yes
0 = no
1 = yes
0 = no
1 = yes
0 = no
1 = yes
0 = no
1 = yes
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
SC28L92
…continued
© NXP B.V. 2007. All rights reserved.
38 of 73