SCC2681AE1N28,112 NXP Semiconductors, SCC2681AE1N28,112 Datasheet - Page 21
![IC DUART 28-DIP](/photos/6/82/68298/568-28-dip_sot117-1_sml.jpg)
SCC2681AE1N28,112
Manufacturer Part Number
SCC2681AE1N28,112
Description
IC DUART 28-DIP
Manufacturer
NXP Semiconductors
Datasheet
1.SCC2681AC1N40112.pdf
(29 pages)
Specifications of SCC2681AE1N28,112
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
3Bit
Voltage - Supply
4.5 V ~ 5.5 V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Cmos
Yes
Mounting Type
Through Hole
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935274498112
SCC2681AE1N28
SCC2681AE1N28
SCC2681AE1N28
SCC2681AE1N28
Philips Semiconductors
Table 5. Baud Rates Extended
NOTE: Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left.
This change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68692 and SCC2698B” in application notes elsewhere in this publication.
The test mode at address H‘A’ changes all transmitters and receivers to the 1 mode and connects the output ports to some internal nodes.
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
Reset can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software or
Receiver Reset in the Normal Mode (Receiver Enabled)
Reset can be accomplished easily by issuing a receiver software or hardware reset followed by a receiver enable. All receiver data,
status and programming will be preserved and available before reset. The reset will NOT affect the programming.
Receiver Reset in the Wake-Up Mode (MR1[4:3] = 11)
hardware reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and
available before reset. The reset will NOT affect other programming.
The reason for this is the receiver is partially enabled when the parity bits are at ‘11’. Thus the receiver disable and reset is bypassed by
the partial enabling of the receiver.
CSR[7:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ACR[7] = 0
I/O2 – 16
I/O2 – 1
38.4 k
134.5
1,200
1,050
2,400
4,800
7,200
9,600
Timer
110
200
300
600
50
Normal BRG
ACR[7] = 1
I/O2 – 16
I/O2 – 1
19.2 k
134.5
1,200
2,000
2,400
4,800
1,800
9,600
Timer
150
300
600
110
75
21
ACR[7] = 0
I/O2 – 16
I/O2 – 1
115.2 k
19.2 k
28.8 k
57.6 k
57.6 k
57.6 k
38.4 k
4,800
1,076
1,050
4,800
9,600
Timer
880
BRG Extended Rates
ACR[7] = 1
I/O2 – 16
I/O2 – 1
SCC2681
115.2 k
14.4 k
28.8 k
57.6 k
57.6 k
14.4 k
19.2 k
7,200
1,076
2,000
4,800
9,600
Timer
880
Product data
SD00097