SC16C654BIEC,551 NXP Semiconductors, SC16C654BIEC,551 Datasheet - Page 26
![IC UART QUAD W/FIFO 64-LFBGA](/photos/6/98/69871/64-lfbga_sot686-1_pkg_sml.jpg)
SC16C654BIEC,551
Manufacturer Part Number
SC16C654BIEC,551
Description
IC UART QUAD W/FIFO 64-LFBGA
Manufacturer
NXP Semiconductors
Type
IrDAr
Datasheet
1.SC16C654BIBS551.pdf
(58 pages)
Specifications of SC16C654BIEC,551
Number Of Channels
4, QUART
Package / Case
64-LFBGA
Features
False-start Bit Detection
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
568-3280
935279071551
SC16C654BIEC-S
935279071551
SC16C654BIEC-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654BIEC,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 14965
Product data sheet
7.2.1 IER versus Receive FIFO interrupt mode operation
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
Table 9:
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reflect the following:
When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C654B/654DB in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
Bit
2
1
0
•
•
•
•
•
•
•
•
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be cleared
when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will indicate any FIFO data errors.
Symbol
IER[2]
IER[1]
IER[0]
Interrupt Enable Register bits description
Description
Receive Line Status interrupt.
Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
logic 0 = disable the transmitter empty interrupt (normal default condition)
logic 1 = enable the transmitter empty interrupt
logic 0 = disable the receiver ready interrupt (normal default condition)
logic 1 = enable the receiver ready interrupt
Rev. 02 — 20 June 2005
SC16C654B/654DB
…continued
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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