SC28L194A1A,529 NXP Semiconductors, SC28L194A1A,529 Datasheet - Page 36

• Manufacturer Part Number: SC28L194A1A,529
• Description: IC UART QUAD SOT188-3
• Manufacturer: NXP Semiconductors

Specifications of SC28L194A1A,529

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Transmit Fifo: 16Byte
• Receive Fifo: 16Byte
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Supply Current: 30mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935261296529; SC28L194A1A-S; SC28L194A1A-S

Philips Semiconductors
RESET CONDITIONS
Device Configuration after Hardware Reset
or CRa cmd=x1F
Cleared registers:
2006 Aug 15
Quad UART for 3.3 V and 5 V supply voltage
Channel Status Registers (SR)
Channel Interrupt Status Registers (ISR)
Channel Interrupt Mask Registers (IMR)
Channel Interrupt Xon Status Register (XISR)
Interrupt Control Register (ICR)
Global Configuration Control Register (GCCR)
Hence the device enters the asynchronous bus cycling mode.
Current Interrupt Register (CIR)
BRG Timer Run Control Register (BRGTCR)
Watch-dog Timer Run Control Register (WDTRCR)
Channel Input/Output Port Configuration Registers (I/OPCR)
Hence all I/O pins have direction = Input after reset
BRG Counter/Timer Registers
36
Clears Modes for:
Disables:
Halts:
Limitations:
Power down
Test modes
Input Port Changed bits
Gang write to Xon or Xoff
Xon/Xoff/Address detection
Receiver error status
Transmitters
Receivers
Interrupts, current and future
BRG Counters
Bus cycle in progress (hardware RESET only)
Minimum RESETN pin pulse width is 10 SClk cycles after Vcc
reaches operational range
The user must allow a minimum of 6 SClk cycles to elapse after
a reset (RESETN pin or CRa initiated) of the device terminates
before initiating a new bus cycle.
SC28L194
Product data sheet