SC28C94A1N,112 NXP Semiconductors, SC28C94A1N,112 Datasheet - Page 17

• Manufacturer Part Number: SC28C94A1N,112
• Description: IC UART QUAD W/FIFO 48-DIP
• Manufacturer: NXP Semiconductors

Specifications of SC28C94A1N,112

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 8 Byte
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Package / Case: 48-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1115-5; 935262535112; SC28C94A1N

Philips Semiconductors
Table 6.
2006 Aug 09
1001
1010
1011
1100
1101
111x
Quad universal asynchronous receiver/transmitter (QUART)
CSR[7:4]
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Negate RTSN. Causes the RTSN output to be negated
(High).
Set Timeout Mode On. The register in this channel will
restart the C/T as each receive character is transferred
from the shift register to the RxFIFO. The C/T is placed in
the counter mode, the START/STOP counter commands
are disabled, the counter is stopped, and the Counter
Ready Bit, ISR[3], is reset.
Only one receiver should use this mode at a time.
However, if both are on, the timeout occurs after both
receivers have been inactive for the timeout. The start of
the C/T will be on the logical ‘OR’ of the two receivers.
See “Timeout Mode Caution” paragraph.
Set MR Pointer to 0.
Disable Timeout Mode. This command returns control of
the C/T to the regular START/STOP counter commands.
It does not stop the counter, or clear any pending
interrupts. After disabling the timeout mode, a ‘Stop
Counter’ command should be issued.
Set Block Error Mode. Sets error bits in states register as
bytes are loaded to the FIFO. Normal byte error reporting
occurs when a byte is read from the FIFO on a per
character basis. This mode enables the error to be set as
the byte is loaded to the FIFO. This allows the control
software to “See” the error as soon as the byte is received.
Block error reporting (enabled by MR0 [5] = 1) accumulates
the error for the entire block of data. This will make it difficult
to locate the error on the particular byte(s) causing the error.
The block error mode of error accumulation is cleared
only by software reset of the individual receiver or by a
hardware reset of the entire chip.
Reserved for testing.
Baud Rate
ACR[7] = 0
I/O2 – 16X
I/O2 – 1X
134.5
1,200
1,050
2,400
4,800
7,200
9,600
38.4k
Timer
110
200
300
600
50
BRG RATE = LOW
ACR[7] = 1
I/O2 – 16X
I/O2 – 1X
1,200
2,000
2,400
4,800
1,800
9,600
Timer
38.4k
19.2k
150
300
600
110
75
ACR[7] = 0
I/O2 – 16X
I/O2 – 1X
230.4K
134.5
3,600
7,200
1,050
14.4K
28.8K
7,200
57.6K
Timer
1200
1800
300
110
17
BRG RATE = HIGH
CSR – Clock Select Register
CSR[7:4] – Receiver Clock Select
When using a 3.6864MHz crystal or external clock input, this field
selects the baud rate clock for the receiver as shown in Table 6.
The receiver clock is always a 16X clock, except for CSR[7:4] =
1111. I/O2x is external input.
CSR[3:0] – Transmitter Clock Select
This field selects the baud rate clock for the transmitter. The field
definition is as shown in Table 6, except as follows:
CSR[3:0]
1 1 1 0
1 1 1 1
CR[3] – Disable Transmitter
This command terminates transmitter operation and resets the
TxRDY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the TxFIFO when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state.
While the transmitter is disabled (or a disable is pending), the
TxFIFO may not be loaded.
CR[2] – Enable Transmitter
Enables operation of the transmitter. The TxRDY and TxEMT status
bits will be asserted.
CR[1] – Disable Receiver
This command terminates operation of the receiver immediately – a
character being received will be lost. However any unread characters
in the RxFIFO area are still available. Disable is not the same as a
“receiver reset”. With a receiver reset any characters not read are
lost. The command has no effect on the receiver status bits or any
other control registers. If the special wake–up mode is programmed,
the receiver operates even if it is disabled (see Wake-up Mode).
CR[0] – Enable Receiver
Enables operation of the receiver. If not in the special wake-up
mode, this also forces the receiver into the search for start bit state.
ACR[7] = 1
I/O2 – 16X
I/O2 – 1X
115.2K
14.4K
28.8K
57.6K
134.5
1,800
3,600
7,200
2,000
1,800
Timer
ACR[7] = 0
I/O3x – 16X
I/O3x – 1X
450
900
110
ACR[7] = 0
I/O2 – 16X
ACR[7] = 1
I/O3x – 16X
I/O3x – 1X
I/O2 – 1X
115.2K
4,800
1,076
19.2K
28.8K
57.6K
1,050
57.6K
4,800
57.6K
9,600
38.4K
Timer
880
TEST 1 = 1
SC28C94
Product data sheet
ACR[7] = 1
I/O2 – 16X
I/O2 – 1X
115.2K
14.4K
28.8K
57.6K
57.6K
14.4K
19.2K
7,200
1,076
2,000
4,800
9,600
Timer
880