SC16C554IB64,157 NXP Semiconductors, SC16C554IB64,157 Datasheet - Page 26
![IC UART QUAD W/FIFO 64-LQFP](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C554IB64,157
Manufacturer Part Number
SC16C554IB64,157
Description
IC UART QUAD W/FIFO 64-LQFP
Manufacturer
NXP Semiconductors
Specifications of SC16C554IB64,157
Number Of Channels
4, QUART
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Transmit Fifo
16Byte
Receive Fifo
16Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1321
935270074157
SC16C554IB64
935270074157
SC16C554IB64
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C554IB64,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11616
Product data
7.4 Interrupt Status Register (ISR)
The SC16C554/554D provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12:
Table 13:
Priority
level
1
2
2
3
4
5
6
Bit
7-6
5-4
3-1
0
ISR[5]
0
0
0
0
0
0
1
Interrupt source
Interrupt Status Register bits description
Symbol
ISR[7-6]
ISR[5-4]
ISR[3-1]
ISR[0]
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
ISR[4]
0
0
0
0
0
1
0
Rev. 04 — 19 June 2003
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
ISR[3]
0
0
1
0
0
0
0
Table 12 “Interrupt source”
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
SC16C554/554D
ISR[0]
0
0
0
0
0
0
0
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY (Transmitter
Holding Register Empty)
MSR (Modem Status
Register)
RXRDY (Received Xoff
signal) / Special character
CTS, RTS change of state
shows the data values
Table
12).
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