SC16C752IB48,157 NXP Semiconductors, SC16C752IB48,157 Datasheet - Page 25
SC16C752IB48,157
Manufacturer Part Number
SC16C752IB48,157
Description
IC DUAL UART 64BYTE 48LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C752IB48157.pdf
(47 pages)
Specifications of SC16C752IB48,157
Number Of Channels
2, DUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270055157
SC16C752IB48
SC16C752IB48
SC16C752IB48
SC16C752IB48
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C752IB48,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11635
Product data
7.7 Modem status register (MSR)
7.8 Interrupt enable register (IER)
This 8-bit register provides information about the current state of the control lines
from the mode, data set, or peripheral device to the processor. It also indicates when
a control input from the modem changes state.
register bit settings per channel.
Table 15:
[1]
The interrupt enable register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from
LOW to HIGH. The INT output signal is activated in response to interrupt generation.
Table 16
Table 16:
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
The primary inputs RI, CD, CTS, DSR are all Active-LOW, but their registered equivalents in the MSR
and MCR (in loop-back) registers are Active-HIGH.
Symbol
IER[7]
IER[6]
IER[5]
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
shows interrupt enable register bit settings.
Modem Status Register bits description
Interrupt Enable Register bits description
[1]
[1]
[1]
Description
CTS interrupt enable.
RTS interrupt enable.
Xoff interrupt.
Rev. 04 — 20 June 2003
Description
CD (Active-HIGH, logical 1). This bit is the complement of the CD input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[3].
RI (Active-HIGH, logical 1). This bit is the complement of the RI input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[2].
DSR (Active-HIGH, logical 1). This bit is the complement of the DSR
input during normal mode. During internal loop-back mode, it is
equivalent MCR[0].
CTS (Active-HIGH, logical 1). This bit is the complement of the CTS
input during normal mode. During internal loop-back mode, it is
equivalent to MCR[1].
changed state. Cleared on a read.
state from LOW to HIGH. Cleared on a read.
changed state. Cleared on a read.
changed state. Cleared on a read.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt.
Logic 0 = Disable the Xoff interrupt (normal default condition).
Logic 1 = Enable the Xoff interrupt.
CD. Indicates that CD input (or MCR[3] in loop-back mode) has
RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed
DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has
CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has
Table 15
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Dual UART with 64-byte FIFO
shows modem status
SC16C752
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