AGLN125V2-VQG100 Actel, AGLN125V2-VQG100 Datasheet - Page 12

• Manufacturer Part Number: AGLN125V2-VQG100
• Manufacturer: Actel

IGLOO nano Device Overview
1 -8
PLL and CCC
Higher density IGLOO nano devices using either the two I/O bank or four I/O bank architectures
provide designers with very flexible clock conditioning capabilities. AGLN060, AGLN125, and
AGLN250 contain six CCCs. One CCC (center west side) has a PLL. The AGLN030 and smaller devices
use different CCCs in their architecture (CCC-GL). These CCC-GLs contain a global MUX but do not
have any PLLs or programmable delays.
For devices using the six CCC block architecture, these are located at the four corners and the
centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east
CCC allow simple clock delay operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections
to the CCC block, which are located near the CCC.
The CCC block has these key features:
Additional CCC specifications:
Global Clocking
IGLOO nano devices have extensive support for multiple clocking domains. In addition to the CCC
and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
I/Os with Advanced I/O Standards
IGLOO nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V,
1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V).
The I/Os are organized into banks with two, three, or four banks per device. The configuration of
these banks determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of various single-data-rate applications for all versions of nano devices and
double-data-rate applications for the AGLN060, AGLN125, and AGLN250 devices.
IGLOO nano devices support LVTLL and LVCMOS I/O standards, are hot-swappable, and support
cold-sparing and Schmitt trigger.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of
a card in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data
undisturbed when the system is powered up, while the component itself is powered down, or
when power supplies are floating.
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Wide input frequency range (f
Output frequency range (f
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used (for PLL only)
Maximum acquisition time is 300 µs (for PLL only)
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL
only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
f
OUT_CCC
(for PLL only)
OUT_CCC
A dv a n c e v 0. 8
IN_CCC
) = 0.75 MHz up to 250 MHz
) = 1.5 MHz up to 250 MHz