AGLN125V2-VQG100 Actel, AGLN125V2-VQG100 Datasheet - Page 63

• Manufacturer Part Number: AGLN125V2-VQG100
• Manufacturer: Actel

Table 2-72 • Input DDR Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD1
DDRISUD2
DDRIHD1
DDRIHD2
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
For specific junction temperature and voltage supply levels, refer to
values.
Commercial-Case Conditions: T
1.2 V DC Core Voltage
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (negedge)
Data Setup for Input DDR (posedge)
Data Hold for Input DDR (negedge)
Data Hold for Input DDR (posedge)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
J
= 70°C, Worst-Case V
A dv a n c e v 0. 3
Description
CC
= 1.14 V
IGLOO nano DC and Switching Characteristics
Table 2-7 on page 2-7
0.93
Std.
0.76
0.94
0.84
0.00
0.00
1.23
1.42
0.00
0.24
0.19
0.31
0.28
TBD
for derating
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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