LM49350RLX/NOPB National Semiconductor, LM49350RLX/NOPB Datasheet - Page 24

• Manufacturer Part Number: LM49350RLX/NOPB
• Description: IC AUDIO SUBSYSTM .8W D 36USMDXT
• Manufacturer: National Semiconductor
• Series: Boomer®r
• Type: Class Dr

Specifications of LM49350RLX/NOPB

• Output Type: 1-Channel (Mono) with Mono and Stereo Headphones
• Max Output Power X Channels @ Load: 2W x 1 @ 4 Ohm; 69mW x 2 @ 32 Ohm
• Voltage - Supply: 2.7 V ~ 5.5 V
• Features: 3D, DAC, Depop, I²C, I²S, Mute, Short-Circuit and Thermal Protection, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 36-MicroSMDxt
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM49350RLX

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13.0 System Control
Method 1. I
13.1 I
In I
SCL and the pin SDA is used for the I
13.3 I
START and STOP bits classify the beginning and the end of
the I
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I
13.4 TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
Register changes take effect at the SCL rising edge during
the last ACK from slave.
2
C mode the LM49350 pin SCL is used for the I
2
C session. START condition is defined as SDA signal
2
2
C SIGNALS
C START AND STOP CONDITIONS
2
C Compatible Interface
th
clock pulse, signifying an acknowledge. A
2
C master always generates
2
C data signal SDA. Both
FIGURE 7. I
FIGURE 6. I
FIGURE 8. I
2
C clock
2
C Start and Stop Conditions
2
C Signals: Data Validity
2
C Chip Address
24
these signals need a pull-up resistor according to I
fication. The I
13.2 I
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.
START and STOP bits. The I
after START condition and free after STOP condition. During
data transmission, I
conditions. First START and repeated START conditions are
equivalent, function-wise.
After the START condition, the I
dress. This address is seven bits long followed by an eight bit
which is a data direction bit (R/W). The LM49350 address is
0011010
“1” indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
2
C DATA VALIDITY
2
. For the eighth bit, a “0” indicates a WRITE and a
2
C slave address for LM49350 is 0011010
20194123
2
20194125
C master can generate repeated START
20194124
2
C bus is considered to be busy
2
C master sends a chip ad-
2
C speci-
2
.