CD82C89 Intersil Corporation, CD82C89 Datasheet
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CD82C89
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CD82C89 Summary of contents
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... Static CMOS circuit design insures low operating power. The advanced Intersil SAJI CMOS process results in perfor- mance equal to or greater than existing equivalent products at a significant power savings. Ordering Information PART NUMBER CP82C89 IP82C89 CS82C89 o o IS82C89 +85 C CD82C89 +125 C ID82C89 MD82C89/B 5962-8552801RA MR82C89/B 5962-85528012A RESB ...
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Functional Diagram S 2 80C86 80C88 S 0 STATUS LOCK CLK CONTROL/ CRQLCK STRAPPING RESB OPTIONS ANYRQST IOB Pin Description PIN SYMBOL NUMBER TYPE decoupling. GND 10 GROUND. S0, S1 18-19 I ...
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Pin Description (Continued) PIN SYMBOL NUMBER TYPE IOB BUS: A strapping option which configures the 82C89 Arbiter to operate in systems having both an IO Bus (Peripheral Bus) and a multi-master system bus. The arbiter requests and ...
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Functional Description The 82C89 Bus Arbiter operates in conjunction with the 82C88 Bus Controller to interface 80C86, 80C88 processors to a multi-master system bus (both the 80C86 and 80C88 are configured in their max mode). The processor is unaware of ...
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Serial Priority Resolving The serial priority resolving technique eliminates the need for the priority encoder-decoder arrangement by daisychain- ing the bus arbiters together, connecting the higher priority bus arbiter’s BPRO (Bus Priority Out) output to the BPRN of the next ...
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RDY2 82C84A/85 CLOCK GENERATOR AEN2 RDY1 READY AEN1 CLK READY CLK 80C86 CPU S0 S1 STATUS (S0, S1, S2) AD0-AD15 A16-A19 S2 OE STB ADDRESS PROCESSOR LATCH LOCAL BUS 82C82/ 82C83H ( DT/R TRANSCEIVER ...
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XACK(I/O BUS) READY CLK 8089 IOP AD0-AD15 A16-A19 I/O COMMAND BUS PROCESSOR LOCAL BUS OE STB ADDRESS I/O LATCH ADDRESS 82C82/ BUS 82C83H ( I/O TRANSCEIVER DATA 82C86H/ BUS 82C87H (2) FIGURE 5. TYPICAL MEDIUM COMPLEXITY ...
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XACK RESIDENT BUS RESIDENT COMMAND BUS PROM OR DECODER OR CMOS HPL (NOTE) RESIDENT ADDRESS BUS RESIDENT DATA BUS FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYSTEM - RESIDENT BUS CONFIGURATION NOTE: By adding another 82C89 arbiter and connecting its ...
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TABLE 1. SUMMARY OF 82C89 MODES, REQUESTING AND RELINQUISHING THE MULTI-MASTER SYSTEM BUS SINGLE LINES FROM 80C86 OR 80C88 OR 8088 IOB MODE ONLY IOB = LOW RESB = LOW I Commands 0 ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications SYMBOL PARAMETER (1) TCLCL CLK Cycle Period (2) TCLCH CLK Low Time (3) TCHCL CLK High Time (4) TSVCH Status Active Setup (5) TSHCL Status Inactive Setup (6) THVCH ...
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AC Test Load Circuits BUSY, CBRQ LOAD CIRCUIT 2.5V 102 OUTPUT FROM TEST DEVICE POINT UNDER TEST 100pF (NOTE) NOTE: Includes Stray and Jig Capacitance AC Testing Input, Output Waveform INPUT V +0.4V IH 1.5V V -0.4V IL 82C89 AEN ...
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Timing Waveform STATE CLK (6) THVCH S2, S1, S0 (12) TCLLL1 LOCK (SEE NOTE 1) SYSB/RESB AEN (SEE NOTE 3) PROCESSOR CLK RELATED BUS CLK RELATED BCLK (18) TBLBRL BREQ #2 BPRN #2 (BPRO #1) BPRO #2 (BPRN #3) BUSY ...
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Burn-In Circuits F7 F13 F14 F12 CC/2 F8 F12 CC/ 2 NOTES 5.5V 0.5V, GND = 4.5V 10 -0.2V to +0.4V IH ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...