MC74F74N Motorola, MC74F74N Datasheet
MC74F74N
Manufacturer Part Number
MC74F74N
Description
Dual d-type positive edge-triggered flip-flop
Manufacturer
Motorola
Datasheet
1.MC74F74N.pdf
(3 pages)
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MC74F74N
Manufacturer:
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MC74F74N
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DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
and complementary (Q, Q) outputs. Information at the input is transferred to
the outputs on the positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
The MC54/74F74 is a dual D-type flip-flop with Direct Clear and Set inputs
ESD > 4000 Volts
Asynchronous Inputs:
FUNCTION TABLE (Each Half)
H = HIGH Voltage Level
L = LOW Voltage Level
t n = Bit time before clock pulse
t n + 1 = Bit time after clock pulse
LOW Input to S D sets Q to HIGH level
LOW Input to C D sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C D and S D makes both Q and Q HIGH
C D1
V CC C D2
14
1
Input
@ t n
D
H
L
CP 1
D 1
CONNECTION DIAGRAM
D 1
13
2
C D1 Q 1
S D1
CP 1
D 2
12
3
Q 1
CP 2
S D1
11
4
S D2
10
Q 1
5
CP 2
D 2
S D2
C D2
Q 2
Q 1
FAST AND LS TTL DATA
9
6
Outputs
@ t n + 1
Q
L
H
Q 2
Q 2
GND
Q 2
8
7
H
Q
L
4-33
2
3
14
14
EDGE-TRIGGERED FLIP-FLOP
14
ORDERING INFORMATION
1
CP 1
1
D 1
MC54/74F74
DUAL D-TYPE POSITIVE
FAST
MC54FXXJ
MC74FXXN
MC74FXXD
S D1
C D1
4
1
1
Q 1
Q 1
LOGIC SYMBOL
V CC = PIN 14
GND = PIN 7
SCHOTTKY TTL
6
5
12
11
Ceramic
Plastic
SOIC
CASE 751A-02
CASE 646-06
CASE 632-08
CERAMIC
N SUFFIX
J SUFFIX
D 2
CP 2
PLASTIC
D SUFFIX
C D2
S D2
SOIC
10
13
Q 2
Q 2
9
8
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MC74F74N Summary of contents
Page 1
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. ...
Page 2
NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. GUARANTEED OPERATING RANGES Symbol Parameter V CC Supply Voltage T A Operating ...
Page 3
AC CHARACTERISTICS Symbol Parameter f max Maximum Clock Frequency t PLH Propagation Delay t PHL PLH Propagation Delay t PHL ...