CD22354AE Intersil Corporation, CD22354AE Datasheet
![no-image](/images/manufacturer_photos/0/3/342/intersil_corporation_sml.jpg)
CD22354AE
Available stocks
Related parts for CD22354AE
CD22354AE Summary of contents
Page 1
... CD22354A and CD22357A are ideally suited for PABX, central office switching system, digital telephones as well as other applications that require accurate A/D and D/A conversions and minimal conversion time. Ordering Information NUMBER CD22354AE CD22357AE FULL-FEATURE PCM CODEC 14 GS XMIT X ...
Page 2
Absolute Maximum Ratings DC Supply-Voltage, (V .-0 Supply-Voltage, (V ...
Page 3
Electrical Specifications 5 - PARAMETER SYMBOL TRANSMIT AND RECEIVE FILTER TRANSFER CHARACTERISTICS Transmit Gain (Relative to Gain at 1020Hz) Input Amplifier Set to Unity Gain Receive Gain (Relative to Gain ...
Page 4
Electrical Specifications PARAMETER SYMBOL AC DISTORTION Signal to Total Distortion STD Xmit Single Frequency Distortion SFD Xmit Intermodulation (End-to-End Measurement) 2-Tone Transmit Delay, Absolute Transmit Envelope Delay Relative to t DAX Receive Delay, Absolute ...
Page 5
Electrical Specifications (Continued) PARAMETER SYMBOL Transmit Input Amplifier Gain, Unity Transmit Gain, Absolute G Receive Gain, Absolute G Electrical Specifications PARAMETER SYMBOL AC NOISE Transmit Noise Receive Noise V+ Power Supply Rejection PSRR Transmit V- Power Supply Rejection PSRR Transmit ...
Page 6
Electrical Specifications PARAMETER SYMBOL AC TIMING Frequency of Master Clocks 1/t Width of Master Clock High t Width of Master Clock Low t Rise Time of Master Clock Fall Time of Master Clock Set-up Time from BCLK High t X ...
Page 7
Electrical Specifications (Continued) PARAMETER SYMBOL Hold Time from 3rd Period of Bit Clock Low to Frame Sync ( Minimum Width of the Frame Sync Pulse (Low Level) NOTE: 1. For short frame sync timing, FS ...
Page 8
Functional Description Power Supply Sequencing Do not apply input signal or load on output before powering up V supply. Care must be taken to ensure that D CC goes on common back plane (with other D chips). D pin cannot ...
Page 9
A rising edge on the receive frame sync, FS PCM data latched in on the next falling edge of the R BCLK . The remaining seven bits are latched on the succes- R sive seven falling ...
Page 10
RM t WWH t FM MCLK R MCLK X t SBFM t SBFM BCLK SFB HBF t DZF t DZF HBF 1 BCLK SFB ...