MC68331MFC16 Motorola, MC68331MFC16 Datasheet
MC68331MFC16
Specifications of MC68331MFC16
Related parts for MC68331MFC16
MC68331MFC16 Summary of contents
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... CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this capability. This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA INC.,1993, 1996 Order this document by MC68331TS/D Rev. 2 MC68331 ...
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... MHz 2 pc tray 44 pc tray 20 MHz 2 pc tray 44 pc tray Order Number SPAKMC331CFC16 MC68331CFC16 SPAKMC331CFC20 MC68331CFC20 SPAKMC331VFC16 MC68331VFC16 SPAKMC331VFC20 MC68331VFC20 SPAKMC331MFC16 MC68331MFC16 SPAKMC331MFC20 MC68331MFC20 SPAKMC331CFV16 MC68331CFV16 SPAKMC331CFV20 MC68331CFV20 SPAKMC331VFV16 MC68331VFV16 SPAKMC331VFV20 MC68331VFV20 SPAKMC331MFV16 MC68331MFV16 SPAKMC331MFV20 MC68331MFV20 MC68331 MC68331TS/D ...
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... Queued Serial Module 5.1 Overview ................................................................................................................................... 51 5.2 Pin Function .............................................................................................................................. 52 5.3 QSM Registers ..........................................................................................................................53 5.4 QSPI Submodule .......................................................................................................................56 5.5 SCI Submodule .........................................................................................................................64 6 General-Purpose Timer Module 6.1 Overview ................................................................................................................................... 70 6.2 Capture/Compare Unit ..............................................................................................................71 6.3 Pulse-Width Modulator ..............................................................................................................74 6.4 GPT Registers ...........................................................................................................................75 7 Summary of Changes MC68331 MC68331TS/D TABLE OF CONTENTS Page MOTOROLA 3 ...
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... Two 16-Bit Free-Running Counters With One Nine-Stage Prescaler — Three Input Capture Channels — Four Output Compare Channels — One Input Capture/Output Compare Channel — One Pulse Accumulator/Event Counter Input — Two Pulse-Width Modulation Outputs — Optional External Clock Input MOTOROLA 4 MC68331 MC68331TS/D ...
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... SIZ0 PE6/SIZ0 DS PE5/DS AS PE4/AS RMC PE3/RMC AVEC PE2/AVEC DSACK1 PE1/DSACK1 DSACK0 PE0/DSACK0 EBI DATA[15:0] DATA[15:0] R/W RESET HALT BERR IRQ[7:1] PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 MODCLK PF0/MODCLK CLKOUT CLOCK XTAL EXTAL TEST TSC TSC QUOT FREEZE/QUOT 331 BLOCK MOTOROLA 5 ...
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... ADDR17 41 ADDR18 42 PQS0/MISO 43 PQS1/MOSI 44 PQS2/SCK 45 PQS3/PCS0/SS 46 PQS4/PCS1 47 PQS5/PCS2 48 PQS6/PCS3 Figure 2 MC68331 132-Pin QFP Pin Assignments MOTOROLA 6 MC68331 V DD 116 115 BGACK/CS2 114 BG/CS1 113 BR/CS0 112 CSBOOT 111 DATA0 110 DATA1 109 DATA2 108 DATA3 V DD 107 V SS 106 105 DATA4 ...
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... MC68331 109 108 107 106 PE4/AS 105 PE6/SIZ0 104 PE7/SIZ1 103 R/W 102 PF0/MODCLK 101 PF1/IRQ1 100 PF2/IRQ2 99 PF3/IRQ3 98 PF4/IRQ4 97 PF5/IRQ5 96 PF6/IRQ6 95 PF7/IRQ7 94 BERR 93 HALT 92 RESET CLKOUT XFC EXTAL XTAL FREEZE/QUOT 80 TSC 79 BKPT/DSCLK 78 IFETCH/DSI 77 IPIPE/DSO 76 RXD 75 PQS7/TXD 331 144-PIN QFP MOTOROLA 7 ...
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... It contains circuitry to support exception processing, address space partition- ing, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communi- cate with one another and with external components through the IMB. The IMB in the MCU uses 24 address and 16 data lines. MOTOROLA 8 GPT SIM ...
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... I/O PE0 — — — — — — O PC[2:0] — — I/O GP4 I/O GP[7:5] — — I/O PF[7:1] I/O PQS0 I/O PF0 I/O PQS1 I/O GP[3:0] I — I — I/O PQS3 I/O PQS[6:4] O — — — — — I/O PE3 MOTOROLA 9 ...
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... Bo O Type B output that can be operated in an open-drain mode 2.4 Signal Characteristics Signal Name ADDR[23:0] AS AVEC BERR BG BGACK BKPT BR CLKOUT CS[10:0] CSBOOT DATA[15:0] DS MOTOROLA 10 Output Input Driver Synchronized Hysteresis — — — — ...
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... Output — Input — Output (Port) Input/Output — Input/Output (Port) Input/Output (Port) Input/Output (Port) Input — Output — Output — Input/Output 0 Output 0 Output 1/0 Input — Input/Output — Output — Input 0 Input — Output — Input — Output — Function MOTOROLA 11 ...
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... Read/Write SCI Receive Data QSPI Serial Clock Size Slave Select Three-State Control SCI Transmit Data External Filter Capacitor MOTOROLA 12 Mnemonic CSBOOT Chip select for external boot startup ROM 16-bit data bus DS During a read cycle, indicates when it is possible for an external device to place data on the data bus. During a write cycle, indi- cates that valid data is on the data bus ...
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... MC68331 MC68331TS/D MOTOROLA 13 ...
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... The “Access” column in the SIM address map below indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the SIMCR. MOTOROLA 14 XTAL ...
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... CHIP-SELECT BASE 1 (CSBAR1) CHIP-SELECT OPTION 1 (CSOR1) CHIP-SELECT BASE 2 (CSBAR2) CHIP-SELECT OPTION 2 (CSOR2) CHIP-SELECT BASE 3 (CSBAR3) CHIP-SELECT OPTION 3 (CSOR3) CHIP-SELECT BASE 4 (CSBAR4) 0 NOT USED NOT USED NOT USED (SYPCR) NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED MOTOROLA 15 ...
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... MCU system protection includes a bus monitor, a HALT monitor, a spurious interrupt monitor, and a software watchdog timer. These functions have been made integral to the microcontroller to reduce the number of external components in a complete control system. MOTOROLA CHIP-SELECT OPTION 4 (CSOR4) ...
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... When FREEZE is asserted, the bus monitor continues to operate When FREEZE is asserted, the bus monitor is disabled. MC68331 MC68331TS/D RESET STATUS HALT MONITOR BUS MONITOR SOFTWARE WATCHDOG TIMER PERIODIC INTERRUPT TIMER SHEN SUPV RESET REQUEST BERR RESET REQUEST IRQ[7:1] 300 SYS PROTECT BLOCK $YFFA00 IARB MOTOROLA 17 ...
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... SYPCR —System Protection Control Register 15 NOT USED RESET: SWE —Software Watchdog Enable 0 = Software watchdog disabled 1 = Software watchdog enabled MOTOROLA 18 Action Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled Show cycles enabled, external arbitration enabled, ...
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... The halt monitor reset can be inhib- ited by the HME bit in the SYPCR. MC68331 MC68331TS/D SWP SWT Ratio Bus Monitor Time-out Period 64 System Clocks 32 System Clocks 16 System Clocks 8 System Clocks MOTOROLA 19 ...
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... PIRQL[2:0] —Periodic Interrupt Request Level The following table shows what interrupt request level is asserted when a periodic interrupt is generat- ed PIT interrupt and an external IRQ signal of the same priority occur simultaneously, the PIT in- terrupt is serviced first. The periodic timer continues to run when the interrupt is disabled. MOTOROLA ...
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... Periodic Interrupt Disabled 001 Interrupt Request Level 1 010 Interrupt Request Level 2 011 Interrupt Request Level 3 100 Interrupt Request Level 4 101 Interrupt Request Level 5 110 Interrupt Request Level 6 111 Interrupt Request Level PTP 0 0 MODCLK 0 0 PIT Period = [(PITM)(Prescaler)(4)]/EXTAL $YFFA24 0 PITM MOTOROLA 21 ...
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... When an external system clock signal is applied (i.e., the PLL is not used), duty cycle of the input is critical, especially at near maximum operating frequencies. The relationship between clock signal duty cycle and clock signal period is expressed: 50% — percentage variation of external clock input duty cycle MOTOROLA 22 V DDSYN 1 XFC 0 ...
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... Clock source is determined by the logic state of the MODCLK pin during reset. SYNCR —Clock Synthesizer Control Register RESET MC68331 MC68331TS/D pin to ensure stable operating frequency. DDSYN [4(Y + 1)(2 SYSTEM REFERENCE EDIV $YFFA04 SLIMP SLOCK RSTEN STSIM STEXT MOTOROLA 23 ...
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... The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). Multiple bus cycles may be required for a transfer to or from an 8-bit port. MOTOROLA 24 MC68331 MC68331TS/D ...
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... Transfer Size 0 1 Byte 1 0 Word 1 1 Three Byte 0 0 Long Word FC1 FC0 Address Space 0 0 Reserved 0 1 User Data Space 1 0 User Program Space 1 1 Reserved 0 0 Reserved 0 1 Supervisor Data Space 1 0 Supervisor Program Space 1 1 CPU Space MOTOROLA 25 ...
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... MCU through the use of the DSACK0 and DSACK1 inputs, as shown in the following table. DSACK1 DSACK0 MOTOROLA 26 Table 10 Effect of DSACK Signals 1 Insert Wait States in Current Bus Cycle 0 Complete Cycle —Data Bus Port Size is 8 Bits 1 Complete Cycle — ...
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... SIZ1, SIZ0, and ADDR0 for that bus cycle. MC68331 MC68331TS/D Byte Order OP0 OP1 OP0 Figure 8 Operand Byte Order OP2 OP3 OP1 OP2 OP0 OP1 OP0 MOTOROLA 27 ...
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... If all parameters match, the appropriate chip-select signal is asserted. Select sig- nals are active low. Refer to the following block diagram of a single chip-select circuit. MOTOROLA 28 Table 11 Operand Alignment ...
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... ASSIGNMENT GENERATOR REGISTER Chip Select Discrete Outputs CSBOOT CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 ECLK TIMING AND PIN PIN DATA REGISTER CHIP SEL BLOCK — — — — PC0 PC1 PC2 PC3 PC4 PC5 PC6 MOTOROLA 29 ...
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... CSPAR1 contains five 2-bit fields that determine the functions of corresponding chip-select pins. CSPAR1[15:10] are not used. These bits always read zero; writes have no effect. CSPAR0 Field Chip Select Signal CSPA1[4] CSPA1[3] CSPA1[2] CSPA1[1] CSPA1[0] MOTOROLA 30 Table 12 Pin Assignment Encodings Description 00 Discrete Output 01 Alternate Function 10 ...
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... ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR CS8/ CS7/ CS6/ ADDR21 ADDR20 ADDR19 CS8 CS7 CS6 CS8 CS7 ADDR19 CS8 ADDR20 ADDR19 ADDR21 ADDR20 ADDR19 $YFFA48 ADDR ADDR BLKSZ $YFFA4C–$YFFA74 ADDR ADDR BLKSZ MOTOROLA 31 ...
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... EBI that an ECLK cycle is pending. BYTE —Upper/Lower Byte Option This field is used only when the chip-select 16-bit port option is selected in the pin assignment register. The following table lists upper/lower byte options. MOTOROLA 32 Block Size Address Lines Compared ...
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... Wait States 0011 3 Wait States 0100 4 Wait States 0101 5 Wait States 0110 6 Wait States 0111 7 Wait States 1000 8 Wait States 1001 9 Wait States 1010 10 Wait States 1011 11 Wait States 1100 12 Wait States 1101 13 Wait States 1110 Fast Termination 1111 External DSACK MOTOROLA 33 ...
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... This is a read/write register. Bit 7 is not used. Writing to this bit has no effect, and it always returns zero when read. PORTC — Port C Data Register 15 NOT USED RESET: MOTOROLA 34 Address Space 00 CPU Space 01 ...
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... DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 Table 16 Port E Pin Assignments Port E Signal Bus Control Signal PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 $YFFA11, $YFFA13 PE4 PE3 PE2 PE1 PE0 $YFFA15 DDE4 DDE3 DDE2 DDE1 DDE0 $YFFA17 SIZ1 SIZ0 AS DS RMC AVEC DSACK1 DSACK0 MOTOROLA 35 ...
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... Data bus pin 9 controls the state of this register following reset. If DATA9 is set to one during reset, the register is set to $FF, which defines all port F pins as interrupt request inputs. If DATA9 is cleared to zero during reset, this register is set to $00, defining all port F pins as I/O pins. MOTOROLA 36 8 ...
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... SIZ[1:0] IRQ[7:1] MODCLK Test Mode Disabled VCO = System Clock Background Mode Disabled Alternate Function (Pin Pulled Low) CSBOOT 8-Bit BR BG BGACK FC0 FC1 FC2 ADDR19 ADDR[20:19] ADDR[21:19] ADDR[22:19] ADDR[23:19] PORTE PORTF Test Mode Enabled EXTAL = System Clock Background Mode Enabled MOTOROLA 37 ...
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... The circuit releases the internal reset line as V pins are initialized. When V DD operation. Clock frequency ramps up to the specified limp mode frequency. The external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse. MOTOROLA 38 Table 19 Module Pin Functions Pin Mnemonic DSI/IFETCH ...
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... IRQ[6:1] are maskable. IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive in order to prevent redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is as- serted, and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted. MC68331 MC68331TS/D ramp time and DD MOTOROLA 39 ...
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... The periodic interrupt timer (PIT) in the SIM can generate internal interrupt requests of specific priority at predetermined intervals. By hardware convention, PIT interrupts are serviced before external inter- rupt service requests of the same priority. Refer to 3.2.7 Periodic Interrupt Timer for more information. MOTOROLA 40 MC68331 ...
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... The test submodule supports scan-based testing of the various MCU modules integrated into the SIM to support production testing. Test submodule registers are intended for Motorola use. Register names and addresses are provided to indicate that these addresses are occupied. SIMTR — System Integration Module Test Register SIMTRE — ...
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... MOTOROLA 42 MC68331 MC68331TS/D ...
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... Central Processor Unit Based on the powerful MC68020, the CPU32 processing module provides enhanced system perfor- mance and also uses the extensive software base for the Motorola M68000 family. 4.1 Overview The CPU32 is fully object code compatible with the M68000 Family, which excels at processing calcu- lation-intensive algorithms and supporting high-level languages ...
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... Figure 11 Supervisor Programming Model Supplement MOTOROLA (USP CCR Figure 10 User Programming Model 0 A7' (SSP (CCR) 0 VBR 2 0 SFC DFC Data Registers Address Registers User Stack Pointer PC Program Counter Condition Code Register Supervisor Stack Pointer SR Status Register Vector Base Register Alternate Function ...
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... Included in the register indirect addressing modes are the capabilities to post-increment, predecrement, and offset. The program counter relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the status register, stack point- er, or program counter. MC68331 MC68331TS MOTOROLA 45 ...
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... BSR label BTST Dn, <ea> # <data>, <ea> CHK <ea>, Dn CHK2 <ea>, Rn CLR <ea> CMP <ea>, Dn CMPA <ea>, An CMPI # <data>, <ea> MOTOROLA 46 Table 20 Instruction Set Summary Operand Size 8 Source Destination 16, 32 Source Destination 8, 16, 32 Source Destination 16, 32 Immediate data 8, 16, 32 Immediate data ...
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... CCR Destination 16 Source CCR 16 SR Destination 16 16 Source SR USP USP Listed registers Destination 16, 32 Source Listed registers 16 Operation Upper bound, CCR shows result 1 PC Destination Destination Destination Destination Destination Destination (SSP); (SSP); (SSP); PC (SP); destination PC (SP EBI; STOP 0 X/C MOTOROLA 47 ...
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... Dn <ea> ROXR Dn, Dn #<data>, Dn <ea> RTD #d 1 RTE none RTR none RTS none SBCD Dn, Dn (An), (An) Scc <ea> 1 STOP #<data> MOTOROLA 48 Operand Size Dn [31 : 24] ( (An ( [31 : 24]; (An ( [15 : 8]; (An Immediate data Destination Destination using DFC 8, 16, 32 Source using SFC 16 16 ...
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... SSP; format/vector offset none SSP 4 SSP; PC vector address PC none If cc true, then TRAP exception 16 set, then overflow TRAP exception none Source 0, to set condition codes 8, 16 SP; (SP) An Operation Destination Destination Destination Destination X Destination MSW LSW Temp Dn Temp (SSP); (SSP); SR (SSP MOTOROLA 49 ...
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... DUMP Fill Memory Block Resume Execution Patch User Code Reset Peripherals No Operation MOTOROLA 50 Read the selected address or data register and return the results through the serial interface. register. The specified system control register is read. All registers that can be read in supervisor mode can be read in background mode ...
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... SUPV bit in the QSMCR. MC68331 MC68331TS/D QSPI INTERFACE LOGIC SCI Figure 12 QSM Block Diagram MISO/PQS0 MOSI/PQS1 SCK/PQS2 PCS0/SS/PQS3 PCS1/PQS4 PCS2/PQS5 PCS3/PQS6 TXD/PQS7 RXD QSM BLOCK MOTOROLA 51 ...
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... The following table is a summary of the functions of the QSM pins when they are not configured for gen- eral-purpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an in- put or output. QSPI Pins PCS0/SSMaster SCI Pins MOTOROLA 52 Table 22 QSM Address Map QSM MODULE CONFIGURATION (QSMCR) ...
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... IARB — Interrupt Arbitration Identification Number The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. Re- fer to 3.8 Interrupts for more information. MC68331 MC68331TS SUPV $YFFC00 IARB MOTOROLA 53 ...
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... Pins used for general-purpose I/O must not be assigned to the QSPI by register PQSPAR. To avoid driving incorrect data, the first byte to be output must be written before DDRQS is configured. DDRQS must then be written to determine the direction of data flow and to output the value contained in register PORTQS. Subsequent data for output is written to PORTQS. MOTOROLA ...
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... DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0 Table 23 QSPAR Pin Assignments PQSPAR Bit Pin Function 0 PQS0 1 MISO 0 PQS1 1 MOSI 0 PQS2 1 SCK 0 PQS3 1 PCS0/SS 0 PQS4 1 PCS1 0 PQS5 1 PCS2 0 PQS6 1 PCS3 0 PQS7 1 TXD $YFFC14 PQS4 PQS3 PQS2 PQS1 PQS0 $YFFC16 $YFFC17 MOTOROLA 55 ...
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... SCI transmitter is enabled, the TXD pin is an output. 5.4 QSPI Submodule The QSPI submodule communicates with external devices through a synchronous serial bus. The QSPI is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola products. A block diagram of the QSPI is shown below. MOTOROLA ...
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... I/O. Refer to the following table for QSPI input and output pins and their functions. MC68331 MC68331TS 80-BYTE QSPI RAM CHIP SELECT 4 COMMAND MSB LSB 8/16-BIT SHIFT REGISTER Rx/Tx DATA REGISTER 2 BAUD RATE GENERATOR Figure 13 QSPI Block Diagram M S MOSI M S MISO PCS0/SS PCS[2:1] SCK QSPI BLOCK MOTOROLA 57 ...
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... MSTR WOMQ BITS RESET SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write this register. The QSM has read-only access. MOTOROLA 58 Mnemonics Mode MISO Master Slave MOSI Master Slave SCK Master Slave PCS[3:1] ...
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... CPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices. CPHA is set at reset. MC68331 MC68331TS/D BITS Bits per Transfer 0000 16 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 MOTOROLA 59 ...
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... If DT equals zero, a standard delay is inserted. Standard Delay after Transfer = [17/System Clock] Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. MOTOROLA 60 SCK Baud Rate = System Clock/(2SPBR) or ...
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... HMIE — HALTA and MODF Interrupt Enable 0 = HALTA and MODF interrupts disabled 1 = HALTA and MODF interrupts enabled HMIE controls CPU interrupts caused by the HALTA status flag or the MODF status flag in SPSR. MC68331 MC68331TS ENDQP LOOPQ HMIE HALT $YFFC1C NEWQP $YFFC1E 0 SPSR MOTOROLA 61 ...
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... CPU. The RAM is divided into three segments: receive data, transmit data, and command control data. Receive data is information received from a serial device external to the MCU. Transmit data is infor- mation stored by the CPU for transmission to an external peripheral. Command control data is used to perform the transfer. Refer to the following illustration of the organization of the RAM. MOTOROLA ...
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... TRANSMIT RAM TRD TRE TRF 53E WORD Figure 14 QSPI RAM DSCK PCS3 — — — DT DSCK PCS3 CR0 540 CR1 CR2 COMMAND RAM CRD CRE CRF 54F BYTE $YFFD00 $YFFD20 $YFFD40 PCS2 PCS1 PCS0* — — — PCS2 PCS1 PCS0* MOTOROLA 63 ...
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... QSPI pin output drivers disabled. The QSPI and associated output drivers must be dis- abled by clearing SPE in SPCR1. 5.5 SCI Submodule The SCI submodule is used to communicate with external devices through an asynchronous serial bus. The SCI is fully compatible with the SCI systems found on other Motorola MCUs, such as the M68HC11 and M68HC05 Families. MOTOROLA 64 ...
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... The following table lists the SCBR settings for standard and maximum baud rates using 16.78-MHz and 20.97-MHz system clocks. MC68331 MC68331TS/D Mnemonics Mode RXD Receiver Disabled Receiver Enabled TXD Transmitter Disabled Transmitter Enabled SCBR Function Not Used Serial Data Input to SCI General-Purpose I/O Serial Data Output from SCI $YFFC08 MOTOROLA 65 ...
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... TXD is an output. If TXD is used as a general-purpose input pin, WOMS has no effect. ILT — Idle-Line Detect Type 0 = Short idle-line detect (start count on first one Long idle-line detect (start count on first one after stop bit(s)) MOTOROLA 66 Table 25 SCI Baud Rates SCBR Value 64 ...
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... The transmitter retains control of the TXD pin until completion of any character transfer in progress when TE is cleared. RE — Receiver Enable 0 = SCI receiver disabled (status bits inhibited SCI receiver enabled MC68331 MC68331TS/D PE Result 0 8 Data Bits 1 7 Data Bits, 1 Parity Bit 0 9 Data Bits 1 8 Data Bits, 1 Parity Bit MOTOROLA 67 ...
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... Register RDR is empty or contains previously read data Register RDR contains new data. RDRF is set when the content of the receive serial shifter is transferred to the RDR. If one or more errors are detected in the received word, flag(s) NF, FE, and/or PF are set within the same clock cycle. MOTOROLA ...
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... SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for 9-bit operation. When it is configured for 8-bit operation, they have no meaning or effect. MC68331 MC68331TS R8/T8 R7/T7 R6/T6 R5/ $YFFC0E R4/T4 R3/T3 R2/T2 R1/T1 R0/ MOTOROLA 69 ...
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... The GPT control register address map is shown below. The “Access” column in the GPT address map indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the GPTMCR. MOTOROLA 70 OC1/PGP3 ...
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... PWM CONTROL A (PWMA) PWM COUNT (PWMCNT) PWMA BUFFER (PWMBUFA) GPT PRESCALER (PRESCL) NOT USED 0 PGP DATA (PORTGP) OC1 ACTION DATA (OC1D) PA COUNTER (PACNT) TIMER CONTROL 2 (TCTL2) TIMER MASK 2 (TMSK2) TIMER FLAG 2 (TFLG2) PWM CONTROL C (PWMC) PWM CONTROL B (PWMB) PWMB BUFFER (PWMBUFB) MOTOROLA 71 ...
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... COMPARATOR TOC2 (HI) TOC2 (LO) = 16-BIT COMPARATOR TOC3 (HI) TOC3 (LO) = 16-BIT COMPARATOR TOC4 (HI) TOC4 (LO) = 16-BIT COMPARATOR TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK I4/O5 16/32 CC BLOCK MOTOROLA 72 TCNT (HI) TCNT (LO) TOI 16-BIT FREE RUNNING TOF COUNTER IC1I IC1F IC2I IC2F IC3I IC3F OC1I OC1F FOC1 OC2I ...
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... PIN DIGITAL FILTER MC68331 MC68331TS/D 512 TO PULSE ACCUMULATOR EXT. TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR CPR2 CPR1 CPR0 256 128 SELECT 8 4 EXT. 128 64 32 SELECT EXT. PPR2 PPR1 PPR0 Figure 17 Prescaler Block Diagram TO CAPTURE/ COMPARE TIMER TO PWM UNIT GPT PRE BLOCK MOTOROLA 73 ...
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... Each PWM can be independently programmed to run in fast or slow mode. The PWM unit has its own 16-bit free-running counter, which is clocked by an output of the nine-stage prescaler (the same prescaler used by the capture/compare unit the clock input pin, PCLK. MOTOROLA 74 16-BIT DATA BUS ...
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... IPL — Interrupt Priority Level Specifies the priority level of interrupts generated by the GPT. IVBA — Interrupt Vector Base Address Most significant nibble of interrupt vector number generated by the GPT when an interrupt service re- quest is acknowledged. MC68331 MC68331TS SUPV IPL IVBA $YFF900 IARB $YFF902 $YFF904 MOTOROLA 75 ...
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... PACTL enables the pulse accumulator and selects either event counting or gated mode. In event count- ing mode, PACNT is incremented each time an event occurs. In gated mode incremented by an internal clock. PAIS — PAI Pin State (Read Only) PAEN — Pulse Accumulator System Enable 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled MOTOROLA ...
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... One on PAI inhibits counting Pulse Accumulator Clock Selected System Clock Divided by 512 Same Clock Used to Increment TCNT TOF Flag from TCNT External Clock, PCLK $YFF914, $YFF916, $YFF918, $YFF91A OL3 OM2 OL2 EDGE4 $YFF90E, $YFF910, $YFF912 $YFF91C $YFF91E EDGE3 EDGE2 EDGE1 MOTOROLA 77 ...
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... Pulse accumulator interrupt disabled 1 = Interrupt requested when PAIF flag is set CPROUT — Compare/Capture Unit Clock Output Enable 0 = Normal operation for OC1 pin 1 = TCNT clock driven out OC1 pin MOTOROLA 78 Action Taken Timer Disconnected from Output Logic Toggle OCx Output Line Clear OCx Output Line to 0 ...
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... Setting a bit in CFORC causes a specific output PWM pins. PWMC sets PWM operating con- ditions. MC68331 MC68331TS/D CPR[2:0] System Clock Divide-By Factor 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 PCLK ICF TOF 0 PAOVF FPWMA FPWMB PPROUT PPR $YFF922 PAIF $YFF924 SFA SFB F1A F1B MOTOROLA 79 ...
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... Div 64 = 328 kHz 110 Div 128 = 131 kHz Div 128 = 164 kHz 111 PCLK F1A — Force Logic Level One on PWMA 0 = Force logic level zero output on PWMA pin 1 = Force logic level one output on PWMA pin MOTOROLA 80 PPR[2:0] System Clock Divide-By Factor 000 2 001 4 ...
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... These read-only registers contain values associated with the duty cycles of the corresponding PWM. Reset state is $0000. PRESCL — GPT Prescaler The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as zeros. Reset state is $0000. MC68331 MC68331TS/D $YFF926, $YFF927 $YFF928 $YFF92A, $YFF92B $YFF92C MOTOROLA 81 ...
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... Expanded and revised QSM section. Made all register diagrams and bit mnemon- ics consistent. Added information concerning SPI and SCI operation. Page 77-89 Expanded and revised GPT section. Made all registerdiagrams and bit mnemonics consistent. Added information concerning input capture, output compare, and PWM operation. MOTOROLA 82 MC68331 MC68331TS/D ...
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... MC68331 MC68331TS/D MOTOROLA 83 ...
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...