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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9's Complementer
NBCD adder to allow BCD subtraction. A BCD number (8–4–2–1 code) is
applied to the inputs (A1 = 2 0 , A2 = 2 1 , A3 = 2 2 , A4 = 2 3 ). If the complement
control (Comp) is low, the BCD number appears at the outputs unmodified.
The complement disable (Comp) allows the complement control to be gated,
or an inverted control signal to be used. If the complement input is high and
the disable input low, the 9’s complement of the number is displayed at the
outputs. The zero control (Z), when high, forces the outputs low regardless of
the state of the other inputs.
with the MC14560B NBCD adder, the complement control becomes an
add/subtract control.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
X = Don’t Care.
REV 3
1/94
MAXIMUM RATINGS*
V in , V out
Symbol
MOTOROLA CMOS LOGIC DATA
I in , I out
The MC14561B 9’s complementer is a companion to the MC14560B
When the MC14561B is used to perform BCD subtraction in conjunction
Z
0
0
0
0
1
Motorola, Inc. 1995
V DD
All Inputs Buffered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
T stg
P D
T L
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic “L” Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
Comp
X
0
0
1
1
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
Comp
X
0
1
1
0
(Voltages Referenced to V SS )
A1
A1
F1
0
Parameter
F2
A2
A2
TRUTH TABLE
0
A2A3 + A2A3
F3
A3
0
A2A3A4
– 0.5 to V DD + 0.5
A4
F4
0
– 0.5 to + 18.0
– 65 to + 150
Value
500
260
10
Straight–through
Complement
Mode
Zero
Unit
mW
mA
_ C
_ C
V
V
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V in and V out should be constrained
to the range V SS
appropriate logic voltage level (e.g., either V SS
or V DD ). Unused outputs must be left open.
This device contains protection circuitry to
Unused inputs must always be tied to an
T A = – 55 to 125 C for all packages.
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
MC14561B
COMP
COMP
V SS
PIN ASSIGNMENT
A1
A2
A3
A4
NC = NO CONNECTION
1
2
3
4
5
6
7
v
(V in or V out )
14
13
12
10
11
9
8
CASE 751A
CERAMIC
CASE 632
CASE 646
D SUFFIX
L SUFFIX
P SUFFIX
PLASTIC
Plastic
Ceramic
SOIC
SOIC
V DD
F1
F2
F3
F4
Z
NC
v
MC14561B
V DD .
1