MPC946 Freescale Semiconductor, Inc, MPC946 Datasheet
MPC946
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MPC946 Summary of contents
Page 1
... Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced HIGH. The MPC946 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. ...
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... Pull Down) TCLK_Sel (Int Pull Up) TCLK0 (Int Pull Up) TCLK1 (Int Pull Down) Dsela (Int Pull Down) Dselb (Int Pull Down) Dselc (Int Pull Down) MR/OE Pinout: 32–Lead TQFP (Top View VCCa 25 Qa2 26 GNDa 27 Qa1 28 MPC946 VCCa 29 Qa0 30 GNDa 31 32 MR/ MOTOROLA LOGIC DIAGRAM ...
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... Maximum Quiescent Supply Current C IN Input Capacitance C pd Power Dissipation Capacitance 1. The MPC946 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section current is a result of internal pull–up/pull–down resistors. AC CHARACTERISTICS ( 3.3V 0.3V) Symbol ...
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... VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC946 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...
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... F D É É SECTION AE– MPC946 DETAIL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS – ...
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... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MPC946/D* 6 MPC946/D TIMING SOLUTIONS BR1333 — Rev 6 ...