DSP56001ARC27 Freescale Semiconductor, Inc, DSP56001ARC27 Datasheet

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... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56001A is an MPU-style general purpose Digital Signal Processor (DSP) composed of an efficient 24-bit DSP core, program and data memories, various peripherals, and support circuitry. The DSP56000 core is fed by on-chip Program RAM, two independent data RAMs, and two data ROMs containing sine, A-law, and -law tables ...

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... Freescale Semiconductor, Inc. SECTION 1 SIGNAL/PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SECTION 4 DESIGN CONSIDERATIONS (INCLUDES NOTES FOR DSP56001 TO DSP56001A DESIGN CONVERSION 4-1 SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 SECTION A ROM TABLE LISTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 FOR TECHNICAL ASSISTANCE: Telephone: Email: Internet: Data Sheet Conventions ...

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... Freescale Semiconductor, Inc. DSP56001A FEATURES Digital Signal Processing Core • Efficient, object code compatible, 24-bit 56000 family DSP engine • 16.5 Million Instructions Per Second (MIPS)—60.6 ns instruction cycle at 33 MHz • Million Operations Per Second (MOPS MHz • Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks • ...

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... Freescale Semiconductor, Inc. DSP56001A Product Documentation Peripheral and Support Circuits • Byte-wide Host Interface (HI) with Direct Memory Access (DMA) support • Synchronous Serial Interface (SSI) to communicate with codecs and synchronous serial devices – 8-, 12-, 16-, and 24-bit word sizes – software-selectable time slots in Network mode • ...

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... Freescale Semiconductor, Inc. Table 1 DSP56001A Documentation Topic DSP56001 Detailed description of the 56001 architecture, 24-bit User’s Manual DSP, memory, peripherals, and instruction set DSP56001A Pin and package descriptions, and electrical and timing Data Sheet specifications Related Documentation Table 2 lists additional documentation relevant to the DSP56001A. ...

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... Freescale Semiconductor, Inc. DSP56001A Product Documentation Table 2 DSP56001A Related Documentation (Continued) Document Name Twin CODEC Expansion Board for the DSP56000 ADS Conference Bridging in the Digital Telecommunications Environment Implementation of Adaptive Controllers Calculating Timing Requirements of External SRAM Low Cost Controller for DSP56001 G.722 Audio Processing ...

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... Freescale Semiconductor, Inc. SIGNAL/PIN DESCRIPTIONS INTRODUCTION DSP56001A signals are organized into twelve functional groups as summarized in Table 1-1. Table 1-1 Signal Functional Group Allocations Functional Group Power (V ) CCX Ground (GND ) X Clock Address Bus Data Bus Bus Control Interrupt and Mode Control Host Interface (HI) Port ...

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... Freescale Semiconductor, Inc. DSP56001A Introduction Power Inputs: V Clock Output CCCK 4 V Internal Logic CCQ 3 V Address Bus CCA 3 V Data Bus CCD V Bus Control CCC CCH V SSI/SCI CCS Grounds: GND Clock CK 4 GND Internal Logic Q 5 GND Address Bus A 6 GND ...

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... Freescale Semiconductor, Inc. POWER Power Names V (2) Internal Logic Power—These lines supply a quiet power source to the oscillator CCQ circuits and the mode control and interrupt lines. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the V power rail ...

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... Freescale Semiconductor, Inc. DSP56001A Clock CLOCK State Signal Signal during Name Type Reset EXTAL Input Input External Clock/Crystal Input—This input should be connected to an external crystal external oscillator. XTAL Output Chip- Crystal Output—This output connects the internal crystal oscillator driven output to an external crystal ...

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... Freescale Semiconductor, Inc. BUS CONTROL State Signal Signal during Name Type Reset PS Output Tri-stated Program Memory Select—PS is asserted low for external program memory access tri-stated when the BG or RESET signal is asserted. DS Output Tri-stated Data Memory Select—DS is asserted low for external data memory access ...

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... Freescale Semiconductor, Inc. DSP56001A Interrupt and Mode Control INTERRUPT AND MODE CONTROL Table 1-8 Interrupt and Mode Control Signals State Signal Signal Name during Type Reset MODA Input Input IRQA MODB Input Input IRQB RESET Input Input 1-6 For More Information On This Product, Signal Description Mode Select A/External Interrupt Request A— ...

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... Freescale Semiconductor, Inc. DO NOT APPLY 10 VOLTS TO ANY PIN OF THE Subjecting any pin of the DSP56001A to voltages in excess of the specified TTL/CMOS levels will permanently damage the device. MOTOROLA For More Information On This Product, CAUTION DSP56001A (including DSP56001A/D, Rev to: www.freescale.com DSP56001A Interrupt and Mode Control ...

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... Freescale Semiconductor, Inc. DSP56001A Host Interface (HI) Port HOST INTERFACE (HI) PORT State Signal Signal during Name Type Reset H0–H7 Input/ Tri-stated Host Data Bus (H0–H7)—This data bus transfers data between the Output PB0–PB7 Input or Output HA0–HA2 Input Tri-stated Host Address 0 – Host Address 2 (HA0–HA2)—These inputs PB8– ...

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... Freescale Semiconductor, Inc. Table 1-9 HI Signals (Continued) State Signal Signal during Name Type Reset HEN Input Tri-stated Host Enable—This input enables a data transfer on the host data bus. PB12 Input or Output HREQ Open Tri-stated Host Request—This signal is used by the Host Interface to request ...

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... Freescale Semiconductor, Inc. DSP56001A Serial Communications Interface Port SERIAL COMMUNICATIONS INTERFACE PORT Table 1-10 Serial Communications Interface (SCI) Signals State Signal Signal Name during Type Reset RXD Input Tri-stated Receive Data (RXD)—This input receives byte-oriented data and PC0 Input or Output ...

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... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE PORT Table 1-11 Synchronous Serial Interface (SSI) Signals State Signal Signal Name during Type Reset SC0 Input or Tri-stated Serial Clock 0 (SC0)—This signal’s function is determined by Output PC3 Input or Output SC1 Input or Tri-stated Serial Clock 1 (SC1)—The SSI uses this bidirectional signal to ...

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... Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface Port Table 1-11 Synchronous Serial Interface (SSI) Signals (Continued) State Signal Signal Name during Type Reset SRD Input Tri-stated SSI Receive Data—This input signal receives serial data and PC7 Input or Output STD Output Tri-stated SSI Transmit Data (STD)— ...

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... Freescale Semiconductor, Inc. SPECIFICATIONS GENERAL CHARACTERISTICS The DSP56001A is fabricated in high-density HCMOS with TTL compatible inputs and outputs. Table 2-1 Absolute Maximum Ratings (GND = 0 V) Rating Supply Voltage All Input Voltages Current Drain per Pin excluding V Storage Temperature Note: This device contains circuitry protecting against damage due to high static voltage or electrical fields ...

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... Freescale Semiconductor, Inc. DSP56001A General Characteristics Table 2-4 Thermal Characteristics for 132-pin CQFP/PQFP Packages Thermal Resistance Junction to Ambient Junction to Case (estimated) Note: 1. See discussion under Design Considerations, Heat Dissipation, page 4-1. 2. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided Printed Circuit Board per SEMI G38-87 in natural convection. SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Road, Mountain View, CA 94043, (415) 964-5111 ...

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... Freescale Semiconductor, Inc. DC ELECTRICAL CHARACTERISTICS Table 2-5 DC Electrical Characteristics Characteristics Supply Voltage 27 MHz 33 MHz Input High Voltage •EXTAL •RESET • MODA, MODB • All other inputs Input Low Voltage • EXTAL • MODA, MODB • All other inputs Input Leakage Current ...

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... Freescale Semiconductor, Inc. DSP56001A AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS The timing waveforms in the AC Electrical Characteristics are tested with a V 0.5 V and a V minimum of 2.4 V for all pins, except EXTAL, IH pins are tested using the input levels set forth in the DC electrical characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal’ ...

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... Freescale Semiconductor, Inc. EXTERNAL CLOCK (EXTAL PIN) The DSP56001A system clock may be derived from the on-chip crystal oscillator as shown in Figure 2- may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically unconnected to the board or socket. The rise and fall times of this external clock should maximum. ...

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... Freescale Semiconductor, Inc. DSP56001A External Clock (EXTAL Pin) EXTAL NOTE: The midpoint is V Figure 2-3 External Clock Timing No Characteristics Frequency of Operation (EXTAL Pin) 1 Clock Input High (46.7% – 53.3% duty cycle) 2 Clock Input Low (46.7% – 53.3% duty cycle) 3 Clock Cycle Time ...

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... Freescale Semiconductor, Inc. RESET, STOP, MODE SELECT, AND INTERRUPT TIMING V = 5.0 V 10% for 27 MHz -40 to +105 ˚ TTL loads number of wait states programmed into the external bus access using BCR (WS = 0–15) Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) ...

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... Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued) Num Characteristics 17 Delay from IRQA, IRQB Assertion to External Memory Access Address Out Valid • Caused by First Interrupt Instruction Fetch • ...

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... Freescale Semiconductor, Inc. Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued) Num Characteristics 22 Delay from General-Purpose Output Valid to Interrupt Request Deassertion for Level- Sensitive Fast Interrupts (See — Note 3) If Second Interrupt Instruction is: • Single Cycle • ...

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... Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued) Num Characteristics 28 Delay from Level-Sensitive IRQA Assertion to Fetch of First Interrupt Instruction (when exiting ‘Stop’) (See Note 1) • ...

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... Freescale Semiconductor, Inc. RESET 9 A0–A15 EXTAL 12 RESET A0–A15, DS, PS, X/Y Figure 2-5 Synchronous Reset Timing RESET MODA, MODB Figure 2-6 Operating Mode Select Timing MOTOROLA For More Information On This Product, RESET, Stop, Mode Select, and Interrupt Timing 10 Figure 2-4 Reset Timing ...

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... Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing A0–A15 IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB Figure 2-7 External Level-Sensitive Fast Interrupt Timing IRQA, IRQB IRQA, IRQB Figure 2-8 External Interrupt Timing (Negative Edge-Triggered) ...

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... Freescale Semiconductor, Inc. CKOUT IRQA, IRQB A0–A15, DS, PS, X/Y Figure 2-9 Synchronous Interrupt from Wait State Timing 25 IRQA A0–A15, DS, PS, X/Y Figure 2-10 Recovery from Stop State Using IRQA IRQA A0–A15, DS, PS, X/Y Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service ...

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... Freescale Semiconductor, Inc. DSP56001A Host I/O (HI) Timing HOST I/O (HI) TIMING V = 5.0 V 10% for 27 MHz; 5 for 33 MHz =-40 to 105 ˚ TTL loads J L Note: Active low lines should be pulled manner consistent with the AC and DC specifications. Table 2-9 Host I/O Timing (27/33 MHz) ...

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... Freescale Semiconductor, Inc. Table 2-9 Host I/O Timing (Continued)(27/33 MHz) (Continued) Num Characteristics 39 HR/W Low Setup Time Before HEN Assertion 40 HR/W Low Hold Time After HEN Deassertion 41 HR/W High Setup Time to HEN Assertion 42 HR/W High Hold Time After HEN/HACK Deassertion ...

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... Freescale Semiconductor, Inc. DSP56001A Host I/O (HI) Timing HREQ (Output) HACK (Input) 41 HR/W (Input) 35 H0–H7 (Output) Figure 2-12 Host Interrupt Vector Register (IVR) Read HREQ (Output) RXH HEN Read (Input HA2–HA0 Address (Input) Valid 41 HR/W (Input H0–H7 Data (Output) Valid ...

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... Freescale Semiconductor, Inc. HREQ (Output) TXH HEN Write (Input HA2–HA0 Address (Input) Valid 39 HR/W (Input) 33 H0–H7 Data (Input) Valid Figure 2-14 Host Write Cycle (Non-DMA Mode) HREQ (Output RXH HEN Read (Input H0–H7 Data (Output) Valid Figure 2-15 Host DMA Read Cycle ...

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... Freescale Semiconductor, Inc. DSP56001A Serial Communication Interface (SCI) Timing SERIAL COMMUNICATION INTERFACE (SCI) TIMING V = 5.0 V 10% for 27 MHz; 5 for 33 MHz =-40 to 105 ˚ TTL loads Synchronous Clock Cycle Time (For internal clock, t SCC Control Register and T ) The minimum t C. Table 2-10 SCI Synchronous Mode Timing (27/33 MHz) ...

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... Freescale Semiconductor, Inc. Table 2-11 SCI Asynchronous Mode Timing Num Characteristics 67 Asynchronous Clock Cycle— t ACC 68 Clock Low Period 69 Clock High Period 70 < intentionally blank > 71 Output Data Setup to Clock Rising Edge (Internal Clock) 72 Output Data Hold After Clock Rising Edge (Internal Clock) ...

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... Freescale Semiconductor, Inc. DSP56001A Serial Communication Interface (SCI) Timing SCLK (Output) 59 TXD RXD SCLK (Input) 63 TXD RXD Figure 2-17 SCI Synchronous Mode Timing 1X SCLK (Output) TXD Note: In the Wired-OR mode, TXD can be pulled Figure 2-18 SCI Asynchronous Mode Timing 2-20 For More Information On This Product, ...

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... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING V = 5.0 V 10% for 27 MHz –40 to 105˚ TTL loads SSI clock cycle time SSICC TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) = Receive Frame Sync ...

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... Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface (SSI) Timing Table 2-12 SSI Timing (Continued) Num Characteristics 89 Data In Hold Time After RXC Falling Edge 90 FSR Input (bl) High Before RXC Falling Edge 91 FSR Input (wl) High Before RXC Falling Edge 92 FSR Input Hold Time ...

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... Freescale Semiconductor, Inc. Table 2-12 SSI Timing (Continued) Num Characteristics 102 FST Input (bl) Setup Time Before TXC Falling Edge 103 FST Input (wl) to Data Out Enable from High Impedance 104 FST Input (wl) Setup Time Before TXC Falling Edge 105 FST Input Hold Time ...

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... Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface (SSI) Timing 81 TXC (Input/ Output) FST (Bit) Out FST (Word) Out Data Out 102 FST (Bit) In FST (Word) In Flags Out Note: In the Network mode, output flag transitions can occur at the start of each time slot within the frame ...

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... Freescale Semiconductor, Inc. 81 SRD (Input/Output) FSR (Bit) Out FSR (Word) Out Data Out 90 FSR (Bit) In FSR (Word) In Flags Out Note: In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. ...

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... Freescale Semiconductor, Inc. DSP56001A External Bus Asynchronous Timing EXTERNAL BUS ASYNCHRONOUS TIMING V = 5.0 V 10% for 27 MHz –40 to 105 ˚ TTL loads Number of Wait States, as determined by BCR ( 15) Capacitance Derating: The DSP56001A external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the external bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y) derates linearly per additional capacitance from 250 pF of loading ...

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... Freescale Semiconductor, Inc. Table 2-13 External Bus Asynchronous Timing (Continued) No. Characteristics 119 Delay from BG Deassertion to Address and Control Bus Enabled 120 Address Valid to WR Assertion • • WS > 0 121 WR Assertion Width • • WS > 0 122 WR Deassertion to Address Not Valid 123 WR Assertion to Data Out Active From High Impedance • ...

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... Freescale Semiconductor, Inc. DSP56001A External Bus Asynchronous Timing Table 2-13 External Bus Asynchronous Timing (Continued) No. Characteristics 128 Input Data Hold Time to RD Deassertion 129 RD Assertion Width • • WS > 0 130 Address Valid to Input Data Valid • • WS > 0 131 Address Valid to RD Assertion ...

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... Freescale Semiconductor, Inc A0–A15 D0–D23 Figure 2-21 Bus Request / Bus Grant Timing A0–A15, DS, PS, X/Y (See Note) RD 120 (See Note) 135 WR 123 D0–D23 Note: During Read-Modify-Write instructions, the address lines do not change state. Figure 2-22 External Bus Asynchronous Timing MOTOROLA For More Information On This Product, ...

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... Freescale Semiconductor, Inc. DSP56001A External Bus Synchronous Timing EXTERNAL BUS SYNCHRONOUS TIMING V = 5.0 V 10% for 27 MHz -40˚ to +105˚ TTL loads J L Capacitance Derating: The DSP56001A external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the external bus pins (A0– ...

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... Freescale Semiconductor, Inc. Table 2-14 External Bus Synchronous Timing (Continued) Num Characteristics Note timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal’s transition are wait state values specified in the BCR. ...

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... Freescale Semiconductor, Inc. DSP56001A Bus Strobe / Wait Timing BUS STROBE / WAIT TIMING V = 5.0 V 10% for 27 MHz –40 to 105˚ TTL loads J L Table 2-15 Bus Strobe / Wait Timing No. Characteristics 150 First CKOUT transition to BS Assertion 151 WT Assertion to first CKOUT transition (setup time) ...

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... Freescale Semiconductor, Inc. Table 2-15 Bus Strobe / Wait Timing (Continued) No. Characteristics 161 Data-In Valid to RD Deassertion (Set Up) Note wait states are also inserted using the BCR and if the number of wait states is greater than two, then specification numbers T156 and T157 can be increased accordingly. ...

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... Freescale Semiconductor, Inc. DSP56001A Bus Strobe / Wait Timing T0 T1 CKOUT 140 A0–A15, PS, DS, X/Y 150 BS 151 WT 143 RD D0–D23 141 WR D0–D23 Note: During Read-Modify-Write Instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. ...

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... Freescale Semiconductor, Inc. PIN-OUT AND PACKAGE INFORMATION This section supplies information about the packages which are available for this product. Diagrams of the pinouts of each package are included, and tables describing the pins allocated to each of the signals described in Table 3-1 through Table 3-5. ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information 18 nc H3/PB3 H2/PB2 nc Orientation Mark H1/PB1 (chamfered edge) GNDH GNDH H0/PB0 nc RXD/PC0 TXD/PC1 SCLK/PC2 nc SC0/PC3 SCK/PC6 GNDQ GNDQ V CCQ V CCQ SC2/PC5 nc STD/PC8 SC1/PC4 nc SRD/PC7 BG/BS nc BR/ X Note: 1. “nc” are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias ...

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... Freescale Semiconductor, Inc GNDN GNDN CCN V CCN A10 nc GNDN GNDN A11 A12 A13 nc A14 A15 Note: 1. “nc” are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias OVERBAR indicates the signal is asserted when the voltage = ground (active low). ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information nc 18 H3/PB3 H2/PB2 nc H1/PB1 GNDH GNDH H0/PB0 nc RXD/PC0 TXD/PC1 SCLK/PC2 nc SC0/PC3 SCK/PC6 GNDQ GNDQ V CCQ V CCQ SC2/PC5 nc STD/PC8 SC1/PC4 nc SRD/PC7 BG/BS nc BR/ X Note: 1. “nc” are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias ...

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... Freescale Semiconductor, Inc Orientation Mark GNDN (On Top Side) GNDN CCN V CCN A10 nc GNDN GNDN A11 A12 A13 nc A14 A15 Note: 1. “nc” are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Orientation Mark D19 D21 D22 MODB/ IRQB B D17 D20 D23 C D15 D18 D D14 D16 GNDD E D13 F D11 D12 G D10 VCCD GNDD A15 N D0 A14 A13 A12 Note: 1. “nc” are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias ...

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... Freescale Semiconductor, Inc HR/W HEN HREQ RXD H0 E TXD GNDH F SCLK SC0 G SCK V GNDQ CCQ H SC2 J STD SRD K SC1 BG/BS L BR/ X Note: 1. “nc” are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information The DSP56001A signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-1. Table 3-1 DSP56001A General Purpose I/O Pin Identification Pin Number 132 pin “FC” PQFP “FE” CQFP ...

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... Freescale Semiconductor, Inc. Table 3-1 DSP56001A General Purpose I/O Pin Identification Pin Number 132 pin “FC” PQFP “FE” CQFP Table 3-2 DSP56001A Signal Identification by Pin Number Pin No. Signal Name A1 D19 A2 D21 A3 D22 A4 MODB/IRQB A5 RESET A6 XTAL A7 HA2/PB10 A8 HA1/PB9 A9 HACK/PB14 A10 ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-2 DSP56001A Signal Identification by Pin Number Pin No. Signal Name A12 H6/PB6 A13 H5/PB5 B1 D17 B2 D20 B4 D23 B5 MODA/IRQA B6 EXTAL B7 GNDQ B8 HA0/PB8 B10 HREQ/PB13 B11 H7/PB7 B12 H4/PB4 B13 H3/PB3 C1 D15 C2 D18 C6 V CCQ ...

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... Freescale Semiconductor, Inc. Table 3-3 DSP56001A Signal Identification by Pin Number Pin No. Signal Name 1 HA2/PB10 2 HA1/PB9 HA0/PB8 6 HACK/PB14 HEN/PB12 9 HR/W/PB11 10 HREQ/PB13 11 H7/PB7 12 V CCH 13 V CCH 14 H6/PB6 15 H5/PB5 16 H4/PB4 H3/PB3 20 H2/PB2 H1/PB1 23 GNDH 24 GNDH 25 H0/PB0 MOTOROLA For More Information On This Product, Pin No. ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-3 DSP56001A Signal Identification by Pin Number Pin No. Signal Name 76 A12 77 A13 A14 80 A15 GNDD 91 GNDD Note: 1. “nc” are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. ...

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... Freescale Semiconductor, Inc. Table 3-4 DSP56001A Identification by Signal Name 132 pin Signal “FC” PQFP or Name “FE” CQFP Pin No A10 71 A11 75 A12 76 A13 77 A14 79 A15 MOTOROLA For More Information On This Product, 88 pin Signal “FC” PQFP or “RC” PGA Name “ ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-4 DSP56001A Identification by Signal Name (Continued) 132 pin Signal “FC” PQFP or Name “FE” CQFP Pin No GNDN 74 GNDQ 33 GNDQ 34 GNDQ 130 GNDQ 131 HA0 5 HA1 2 HA2 1 HACK 6 HEN 8 HR/W 9 HREQ 10 IRQA ...

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... Freescale Semiconductor, Inc. Table 3-4 DSP56001A Identification by Signal Name (Continued) 132 pin Signal “FC” PQFP or Name “FE” CQFP Pin No. IRQB 121 MODA 123 MODB 121 NMI none PB0 25 PB1 22 SC1 40 SC2 37 SCK 32 SCLK 29 SRD 42 STD 39 TXD 28 V 100 CCD ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-4 DSP56001A Identification by Signal Name (Continued) 132 pin Signal “FC” PQFP or Name “FE” CQFP Pin No X/Y 48 XTAL 126 Power and ground pins have special considerations for noise immunity. See the section Design Considerations ...

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... Freescale Semiconductor, Inc. Table 3-5 DSP56001A Power Supply Pins (Continued) 132 pin “FC” PQFP or “FE” CQFP Pin No. 100 101 90 91 111 112 35 36 128 129 33 34 130 131 MOTOROLA For More Information On This Product, 88 pin “RC” PGA Power Supply Pin No ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information VIEW 0.016 H L 0.010 T L TIPS 0.012 H L 0.002 132X M 0.008 U D 132X M 0.008 T L-M N SECTION AA-AA Figure 3-7 132-pin Plastic Quad Flat Pack (PQFP) Mechanical Information 3-18 For More Information On This Product, ...

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... Freescale Semiconductor, Inc PIN 1 L IDENT 0.008 4X 33 TIPS 0. 132X VIEW AE Figure 3-8 132-pin Ceramic Quad Flat Pack (CQFP) Mechanical Information MOTOROLA For More Information On This Product, 117 VIEW AC 3 PLACES 116 L-N M VIEW AE NOTES: SEATING PLANE 1. 2. 0.004 T 3 ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information SEATING -T- PLANE -A- -B- C Figure 3-9 88-pin Pin Grid Array (PGA) Mechanical Information Orientation Marks 3-20 For More Information On This Product, - 0.003 T A MATRIX M 0.010 X PINS Top View Figure 3-10 PGA Shipping Tray DSP56001A/D, Rev to: www ...

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... Freescale Semiconductor, Inc. Orientation Marks Figure 3-11 PQFP Shipping Tray Orientation Marks Figure 3-12 CQFP Shipping Tray MOTOROLA For More Information On This Product, Top View Top View DSP56001A/D, Rev to: www.freescale.com DSP56001A Pin-out and Package Information 4 9 AA1132 AA0897 3-21 ...

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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information 3-22 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. DESIGN CONSIDERATIONS SUBSTITUTING THE DSP56001A FOR THE DSP56001 This section highlights the differences between the DSP56001 and DSP56001A that need to be taken into consideration when substituting the DSP56001A for the DSP56001. New designs should use the DSP56002 due to its enhanced features and speed. ...

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... Freescale Semiconductor, Inc. DSP56001A Substituting the DSP56001A for the DSP56001 Software/Application Considerations Software written for the DSP56001 will generally run unmodified on the DSP56001A. There are, however, certain differences which should be noted. Users should consider the impact these differences may have on each application. ...

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... Freescale Semiconductor, Inc. Table 4-1 Illegal Instructions Instruction Symbol — DEBUG DO NOT USE — DEBUGcc DO NOT USE DEC INC MAC #iiii MPY #iiii MACR #iiii MPYR #iiii MOVEP IMMEDIATE MOVEP Immediate instructions take 3 instruction cycles on the DSP56001. On the DSP56001A, these instructions take only 2 instruction cycles. DSP56001 software that is dependent on the timing of this form of the MOVEP instruction must be modified when ported to the DSP56001A ...

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... Freescale Semiconductor, Inc. DSP56001A Substituting the DSP56001A for the DSP56001 CONTROL REGISTERS The OMR and the Status Register on the DSP56001A have been altered from those on the DSP56001. Refer to Table 4-2 for details of these alterations. Table 4-2 Summary of Control Register Differences DSP56001 ...

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... Freescale Semiconductor, Inc. HEAT DISSIPATION The average chip junction temperature, T Equation Where ambient temperature package thermal resistance, junction-to-ambient, C INT I watt — chip internal power INT power dissipation on input and output pins I/O For most applications P < P I/O INT P and T ( neglected) is: ...

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... Freescale Semiconductor, Inc. DSP56001A Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. ...

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... Freescale Semiconductor, Inc. POWER CONSUMPTION Power dissipation is a key issue in portable DSP applications. The following describes some factors that affect current consumption. Current consumption is described by the formula: Equation where : C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle For example, for an address pin loaded with capacitance and operating at 5.5V with a 33 MHz clock, toggling at its maximum possible rate (which is 8 ...

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... Freescale Semiconductor, Inc. DSP56001A Host Port Considerations Host Programming Considerations UNSYNCHRONIZED READING OF RECEIVE BYTE REGISTERS When reading receive byte registers, RXH or RXL, the host program should use interrupts or poll the RXDF flag, which indicates that data is available. This assures that the data in the receive byte registers will be stable ...

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... Freescale Semiconductor, Inc. DSP Programming Considerations SYNCHRONIZATION OF STATUS BITS FROM HOST TO DSP DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. (Refer to the User’ ...

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... Freescale Semiconductor, Inc. DSP56001A Application Examples APPLICATION EXAMPLES The lowest cost DSP56001A-based system is shown in Figure 4-1. It uses no run time external memory and requires only two chips, the DSP56001A and a low cost EPROM. The EPROM read access time should be less than 780 nanoseconds when the DSP56001A is operating at a clock rate of 20 ...

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... Freescale Semiconductor, Inc. A system with external data RAM memory requires no glue logic to select the external EPROM from Bootstrap mode used to enable the EPROM and DS is used to enable the high speed data memories, as shown in Figure 4- IRQB IRQA RESET Note: 1. All resistors are 15 K unless noted otherwise. ...

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... Freescale Semiconductor, Inc. DSP56001A Application Examples Figure 4-3 shows the DSP56001A bootstrapping via the Host Port from an MC68000 IRQB IRQA RESET Note: 1. All resistors are 15 K unless noted otherwise. 2. When in Reset, IRQA and IRQB must be deasserted by external peripherals. Figure 4-3 DSP56001A Host Bootstrap Example—Mode 5 ...

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... Freescale Semiconductor, Inc. In Figure 4-4, the DSP56001A is operated in Mode 3 with external program memory and the reset vector at location $0000. The programmer can overlay the high-speed on-chip Program RAM with DSP algorithms by using the MOVEM instruction IRQB IRQA RESET Note: 1. All resistors are 15 K unless noted otherwise. ...

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... Freescale Semiconductor, Inc. DSP56001A Application Examples Figure 4-5 shows a circuit that waits until V a 75,000 T oscillator stabilization delay required for the on-chip oscillator (only required for an external oscillator). This insures that the DSP is operational and stable before releasing the reset signal. ...

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... Freescale Semiconductor, Inc. Figure 4-6 shows the DSP56001A connected to the bus of an IBM-PC computer. This circuit is complete and does not require external ROM or RAM to load and execute code from the PC. The PAL equations and other details of this circuit are available in the application report entitled “ ...

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... Freescale Semiconductor, Inc. DSP56001A Application Examples 4-16 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...

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... Package Type DSP56001A Ceramic Pin-Grid Array (PGA) Plastic Quad Flat Pack (PQFP) Ceramic Quad Flat Pack (CQFP) MOTOROLA For More Information On This Product, SECTION 5 Frequency Pin Count (MHz) 88 132 132 DSP56001A/D, Rev to: www.freescale.com Order Number 27 DSP56001ARC27 33 DSP56001ARC33 27 DSP56001AFC27 33 DSP56001AFC33 27 DSP56001AFE27 33 DSP56001AFE33 5-1 ...

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... Freescale Semiconductor, Inc. DSP56001A 5-2 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. ROM TABLE LISTINGS The data ROM in the 56001A contains numeric tables. Table A-1 contains the -law and A-law expansion table, stored in X-ROM from address X:$100. Table A-2 contains the sine wave table, stored in Y-ROM from address Y:$100. MU-LAW / A-LAW EXPANSION TABLES ...

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... Freescale Semiconductor, Inc. ROM Table Listings mu-Law / A-Law Expansion Tables M_2E DC $10FC00 ; 1087 M_2F DC $0FFC00 ; 1023 M_30 DC $0F3C00 ; 975 M_31 DC $0EBC00 ; 943 M_32 DC $0E3C00 ; 911 M_33 DC $0DBC00 ; 879 M_34 DC $0D3C00 ; 847 M_35 DC $0CBC00 ; 815 M_36 DC $0C3C00 ; 783 M_37 DC $0BBC00 ; 751 M_38 ...

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... Freescale Semiconductor, Inc. A_80 DC $158000 ; 688 A_81 DC $148000 ; 656 A_82 DC $178000 ; 752 A_83 DC $168000 ; 720 A_84 DC $118000 ; 560 A_85 DC $108000 ; 528 A_86 DC $138000 ; 624 A_87 DC $128000 ; 592 A_88 DC $1D8000 ; 944 A_89 DC $1C8000 ; 912 A_8A DC $1F8000 ; 1008 A_8B DC $1E8000 ; 976 A_8C DC $198000 ...

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... Freescale Semiconductor, Inc. ROM Table Listings mu-Law / A-Law Expansion Tables A_D2 DC $007800 ; A_D3 DC $006800 ; A_D4 DC $001800 ; A_D5 DC $000800 ; A_D6 DC $003800 ; A_D7 DC $002800 ; A_D8 DC $00D800 ; A_D9 DC $00C800 ; A_DA DC $00F800 ; A_DB DC $00E800 ; A_DC DC $009800 ; A_DD DC $008800 ; A_DE DC $00B800 ; A_DF DC $00A800 ; A_E0 DC $056000 ; 172 ...

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... Freescale Semiconductor, Inc. SINE WAVE TABLE This sine wave table is normally used by FFT routines that use bit-reversed address pointers. This table can be used for up to 512 point FFTs; however, for larger FFTs, the table must be copied to a different memory location to allow the Reverse-carry addressing mode to be used (see REVERSE-CARRY MODIFIER (Mn = $0000) in the DSP56001 User’ ...

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... Freescale Semiconductor, Inc. ROM Table Listings Sine Wave Table S_36 DC $7C29FC ; +0.9700313210 S_37 DC $7CE3CF ; +0.9757022262 S_38 DC $7D8A5F ; +0.9807853103 S_39 DC $7E1D94 ; +0.9852777123 S_3A DC $7E9D56 ; +0.9891765118 S_3B DC $7F0992 ; +0.9924796224 S_3C DC $7F6237 ; +0.9951847792 S_3D DC $7FA737 ; +0.9972904921 S_3E DC $7FD888 ; +0.9987955093 S_3F DC $7FF622 ; +0.9996988773 S_40 DC $7FFFFF ...

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... Freescale Semiconductor, Inc. S_88 DC $E70748 ; -0.1950902939 S_89 DC $E3F47E ; -0.2191012055 S_8A DC $E0E607 ; -0.2429800928 S_8B DC $DDDC5B ; -0.2667128146 S_8C DC $DAD7F4 ; -0.2902846038 S_8D DC $D7D947 ; -0.3136816919 S_8E DC $D4E0CB ; -0.3368898928 S_8F DC $D1EEF6 ; -0.3598949909 S_90 DC $CF043B ; -0.3826833963 S_91 DC $CC210D ; -0.4052414000 S_92 DC $C945E0 ; -0.4275551140 S_93 DC $C67323 ; -0.4496113062 S_94 DC $C3A946 ...

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... Freescale Semiconductor, Inc. ROM Table Listings Sine Wave Table S_DA DC $99307F ; -0.8032075167 S_DB DC $9B1777 ; -0.7883464098 S_DC DC $9D0DFE ; -0.7730104923 S_DD DC $9F13C8 ; -0.7572088242 S_DE DC $A12883 ; -0.7409511805 S_DF DC $A34BDF ; -0.7242470980 S_E0 DC $A57D86 ; -0.7071068287 S_E1 DC $A7BD23 ; -0.6895405054 S_E2 DC $AA0A5B ; -0.6715589762 S_E3 DC $AC64D5 ; -0.6531729102 S_E4 DC $AECC33 ...

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... Freescale Semiconductor, Inc. Mfax is a trademark of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...