AT45DB321C-TI ATMEL Corporation, AT45DB321C-TI Datasheet

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... RapidS for applications requiring very high speed operations. Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addition to the 33-megabit main memory, the AT45DB321C also contains two SRAM buffers of 528 bytes each. The buffers allow the receiving of data while a page in the main page Memory is being reprogrammed, as well as writing a continuous data stream ...

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... To allow for simple in-system reprogrammability, the AT45DB321C does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321C is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...

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... RDY/BUSY 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB321C is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis ...

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... The maximum SCK frequency allowable for the Continuous Array Read is defined by the f specification. The Continuous Array Read bypasses both data buffers and leaves the con- CAR tents of the buffers unchanged. AT45DB321C 4 Section 13.6 on page 25. The next 13 bits (PA12-PA0) of the 3387M–DFLASH–2/08 ...

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... If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low-to-high transition is detected on the CS pin. 3387M–DFLASH–2/08 AT45DB321C specification. The Main Memory Page Read bypasses SCK 5 ...

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... When a low-to-high transition occurs on the CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a max- imum time of t the part is busy. AT45DB321C 6 . During this time, the status register and the RDY/BUSY pin will indicate that BE ...

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... AT45DB321C PA4 PA3 PA2 PA1 • • • • • • • • • • • ...

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... If bit then the device busy state. There are many operations that can cause the device busy state: Main Memory Page to Buffer Transfer, Buffer to Main Memory Page Program with Built-in Erase, Buffer to AT45DB321C 8 ), the status register will indicate that the part is busy. On completion of the com- ...

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... The device density is indicated using bits and 2 of the status register. For the AT45DB321C, the four bits are 1, The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...

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... Protected Unprotected Table 6-1. Sectors 0a, 0b Unprotected Protect Sector 0a (Page 0-7) Protect Sector 0b (Page 8-511) Protect Sectors 0a, 0b (Page 0-511) Note: AT45DB321C 10 “Write Protect (WP)” on page 15 Sector 0 (0a, 0b): 0a (Page 0-7) Bit Default value for devices shipped from Atmel is 00H. for more information. ...

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... Read Sector Protection Register Note: 3387M–DFLASH–2/08 Byte 1 ). The Ready/Busy status will indicate that the device is P Next generation devices of the “D” family will not require the 32 don’t care clock cycles. AT45DB321C ). The Ready/Busy status will indicate PE Byte 2 Byte 3 3DH 2AH ...

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... Sector Protection Register is reprogrammed), then the application will need to limit this practice. Instead, a combination of temporarily unprotecting indi- vidual sectors along with disabling sector protection completely will need to be implemented by the application to ensure that the endurance limits of the device are not exceeded. AT45DB321C 12 3387M–DFLASH–2/08 ...

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... Bit 1 Bit 27H 00H 1FH Manufacturer ID Device ID Device ID Byte n Byte 1 Byte 2 AT45DB321C Manufacturer ID 1FH = Atmel Family Code 001 = DataFlash Density Code 00111 = 32-Mbit MLC Code 000 = 1-bit/Cell Technology Product Version 00000 = Initial Version Byte Count 00H = 0 Bytes of Information 00H Data Data ...

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... Security Register The AT45DB321C contains a specialized register that can be used for security purposes in sys- tem design. The Security Register is a unique 128-byte register that is divided into two portions. The first 64 bytes (byte 0 to byte 63) of this page are allocated as a one-time user programmable space ...

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... Atmel with the contents of the Sector Protection Register pre-programmed with “00H” (unprotect). The user can reprogram the Sector Protection Register to change which sec- tors will be protected by the WP pin. 3387M–DFLASH–2/08 AT45DB321C ) would enable the sector pro- WPE 15 ...

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... The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. During Page Erase and Block Erase, read and write operations can be performed to both buffers. AT45DB321C 16 2 Disable Sector Protection Command – ...

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... The process will continue until the device is erased or pro- grammed successfully. In order to optimize the erase and programming time, fixed timing should not be used. Instead, the RDY/BUSY bit of the status register or the RDY/BUSY pin should be monitored. 3387M–DFLASH–2/ the minimum datasheet value, the system CC 8. AT45DB321C “Auto 17 ...

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... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB321C 18 SCK Mode RapidS Mode Inactive Clock Polarity Low or High RapidS Mode ...

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... The Security Register Program command utilizes data stored in Buffer 1. Therefore, this command must be used in conjunc- tion with the Buffer 1 write command. See 3387M–DFLASH–2/08 (1) (1) “Security Register” on page 14 AT45DB321C SCK Mode Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 ...

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... P 59H 60H 61H 68H 77H 81H 82H 83H 84H 85H 86H 87H 88H 89H 9AH 9FH D2H D4H D6H D7H E8H Note Reserved Bit Page Address Bit Byte/Buffer Address Bit Don’t Care AT45DB321C 20 Address Byte Address Byte N/A N ...

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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB321C 0° 70° C -40° 85° C 2.7V to 3.6V Min Typ Max ...

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... The device uses an adaptive algorithm during program and erase operations. Use the RDY/BUSY bit of the status register or the RDY/BUSY pin to determine whether the program or erase operation has completed. Fixed timing should not be used. 3. Value are based on device characterization, not 100% tested in production. AT45DB321C 22 Min ...

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... Waveform 1 – SPI Mode 0 Compatible (for Frequencies MHz) CS SCK HIGH IMPEDANCE SO SI 3387M–DFLASH–2/08 3.0V AC 1.5V 0V DEVICE UNDER TEST period. These timing waveforms are valid over the full frequency range (max CSS VALID OUT VALID IN AT45DB321C AC MEASUREMENT LEVEL Timing waveforms 1 and 2 conform to Rap CSH t DIS HIGH IMPEDANCE 23 ...

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... Waveform 2 – SPI Mode 3 Compatible (for Frequencies MHz SCK HIGH 13.3 Waveform 3 – RapidS Mode 0 (for all Frequencies) CS SCK HIGH IMPEDANCE SO SI 13.4 Waveform 4 – RapidS Mode 3 (for all Frequencies SCK HIGH AT45DB321C CSS VALID OUT VALID CSS VALID OUT ...

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... For densities larger than 32M bits, the “r” bit becomes the most significant Page Address bit for the appropriate density. 3387M–DFLASH–2/08 CMD 8 bits 8 bits Page Address Byte/Buffer Address (PA12-PA0) (BA9-BA0/BFA9-BFA0) AT45DB321C t t REC t RST HIGH IMPEDANCE 8 bits LSB CSS 25 ...

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... Buffer Write CS SI CMD 14.3 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB321C 26 FLASH MEMORY ARRAY BUFFER 1 TO THROUGH BUFFER 2 MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1 BUFFER 1 WRITE I/O INTERFACE ...

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... FLASH MEMORY ARRAY MAIN MEMORY PAGE READ I/O INTERFACE SO PA5-0, BA9-8 BA7-0 X Starts reading page data into buffer CMD r , PA12-6 PA5- X···X, BFA9-8 BFA7-0 AT45DB321C MAIN MEMORY PAGE TO BUFFER 2 BUFFER 2 (528 BYTES) BUFFER 2 READ n 1st byte read ...

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... Detailed Bit-level Read Timing – RapidS Serial Interface Mode 0 15.4.1 Continuous Array Read (Opcode: E8H) CS SCK HIGH IMPEDANCE SO 15.4.2 Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE 15.4.3 Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE AT45DB321C DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE LSB ...

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... Continuous Array Read (Opcode: E8H) CS SCK HIGH IMPEDANCE SO 3387M–DFLASH–2/ MSB MSB DATA OUT AT45DB321C STATUS REGISTER OUTPUT LSB DON’T CARE BYTE FOR FREQ. OVER 25 MHz PRODUCT ID OUTPUT LSB MSB MANUFACTURER ID LSB MSB BIT 4223 BIT PAGE n PAGE n MSB ...

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... Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE 15.5.3 Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE 15.5.4 Status Register Read (Opcode: D7H) CS SCK COMMAND OPCODE HIGH IMPEDANCE SO AT45DB321C HIGH IMPEDANCE HIGH IMPEDANCE MSB DATA OUT MSB DATA OUT ...

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... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3387M–DFLASH–2/ START provide address (82H, 85H) END AT45DB321C PRODUCT ID OUTPUT MSB LSB MANUFACTURER ID and data BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) 17 ...

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... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB321C 32 START ...

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... PA9 PA8 PA7 PA6 • • • • • • • • • • • • AT45DB321C PA5 PA4 PA3 PA2 - PA0 • • • • • • • • • • • • Sector • • • ...

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... Plastic Thin Small Outline Package (TSOP) 28R 28-lead, 0.330” Wide, Plastic Gull Wing Small Outline Package (SOIC) AT45DB321C 34 Ordering Code AT45DB321C-CC AT45DB321C-CNC AT45DB321C-TC AT45DB321C-CI AT45DB321C-TI Ordering Code AT45DB321C-CU AT45DB321C-CNU AT45DB321C-TU (1) Ordering Code AT45DB321C-RC AT45DB321C-RU Package Type Package Operation Range ...

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... San Jose, CA 95131 R 3387M–DFLASH–2/ Ball Corner e 2.00 REF Ø TITLE 24C3, 24-ball ( Array), 1.0 mm Pitch 1.20 mm, Chip-scale Ball Grid Array Package (CBGA) AT45DB321C A1 A Side View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL E 5.90 6.00 6.10 E1 4.0 TYP D 7.90 8 ...

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... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321C 36 D Top View Side View Pin1 Pad Corner L1 ...

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... Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3387M–DFLASH–2/08 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) AT45DB321C 0º ~ 5º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – ...

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... B PIN 0º ~ 8º Note: 1. Dimensions D and E1 do not include mold Flash or protrusion. Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321C TITLE 28R, 28-lead, 0.330" Body Width, Plastic Gull Wing Small Outline (SOIC) COMMON DIMENSIONS ...

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... Revision History Revision Level – Release Date L – June 2006 M – February 2008 3387M–DFLASH–2/08 History Added 28-lead SOIC pinout diagram on page 2. Moved to Mature Products. AT45DB321C 39 ...

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