CY7C4255V-10ASC Cypress Semiconductor Corporation., CY7C4255V-10ASC Datasheet
CY7C4255V-10ASC
Related parts for CY7C4255V-10ASC
CY7C4255V-10ASC Summary of contents
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... Features • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • (CY7C4255V) • 16K x 18 (CY7C4265V) • 32K x 18 (CY7C4275V) • 64K x 18 (CY7C4285V) • 0.35 micron CMOS for optimum speed/power • ...
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... CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. 7C4255/65/75/85V-10 7C4255/65/75/85V-15 100 CY7C4265V 16K x 18 64-pin 10x10 TQFP 64-pin 10x10 TQFP CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V GND ...
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... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual-Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V /SMODE is tied CC /SMODE is tied to V ...
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... IH < Com’l 30 Ind Com’l 4 Ind Test Conditions T = 25° MHz 3.3V CC CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Ambient [3] Temperature V CC 0°C to +70°C 3.3V ±300 mV –40°C to +85°C 3.3V ±300 mV 7C4255/65/75/ 7C4255/65/75/ 85V-15 85V-25 Min. Max. Min. Max. Unit 2.4 2 ...
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... Min. Max. Min. 100 4.5 4.5 3 [12 OHZ CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V ALL INPUT PULSES 90% 90% 10% 10 4287V–5 200 2.0V ALL INPUT PULSES 90% 90% 10% 10 4275V–7 7C4255/65/75/85V -15 -25 Max. Min. Max. Unit 66.7 40 ...
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... Document #: 38-06012 Rev. *A 7C4255/65/75/85V 7C4255/65/75/85V -10 Min. Max. Min. [12 /SMODE 4.5 6 PAF(E) CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 7C4255/65/75/85V -15 -25 Max. Min. Max. Unit ...
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... A VALID DATA t OE [15] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V NO OPERATION t WFF 4275V–8 t REF t OHZ 4275V–9 Page ...
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... Document #: 38-06012 Rev RSR t RSF t RSF t RSF [18] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V [17] OE=1 OE=0 4275V– [19 4275V–11 (maximum) = either 2 FRL CLK SKEW2 Page [+] Feedback ...
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... WCLK [14] t SKEW1 D – WFF FF WEN RCLK t ENH t ENS REN LOW DATA IN OUTPUT REGISTER Q – Document #: 38-06012 Rev. *A CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V ENS REF REF SKEW2 [14 SKEW1 DATA WRITE t WFF t ENS DATA READ t ENH ...
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... HALF FULL OR LESS RCLK REN Programmable Almost Empty Flag Timing t CLKH WCLK WEN [20] PAE RCLK REN Note: 20. PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06012 Rev. *A CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V t CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE ENS ...
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... CY7C4285V. 25. PAF is offset = m. 26. 8192 m words in CY7C4255V, 16384 m words in CY7C4265V, 32768 m words in CY7C4275V, and 65536 27. 8192 ( words in CY7C4255V, 16384 ( words in CY7C4265V, 32768 ( words in CY7C4275V, and 65536 ( words in CY7C4285V. Document #: 38-06012 Rev CLKL t ENH ...
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... SKEW3 t ENS t CLKL t ENH t DH PAF OFFSET (m 1) words of the FIFO when PAF goes LOW. , then PAF may not change state until the next WCLK rising edge. SKEW3 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V [26] t [29] PAF synch t t ENS ENH 4275V–18 PAE OFFSET – D ...
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... Read from Last Physical Location. Document #: 38-06012 Rev CLKL t ENH t A UNKNOWN PAE OFFSET Note Note Note XIS CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PAF OFFSET PAE OFFSET 4275V–20 4275V–21 4275V–22 4275V–23 Page [+] Feedback ...
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... Clocks are free-running in this case. 33. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 34. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06012 Rev. *A CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V t XI ...
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... Empty. See Table 2 for a description of programmable flags. When the SMODE pin is tied LOW, the PAF flag signal transi- tion is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V [35] Selection ...
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... RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C4255/65/75/85Vs. RESET (RS) 18 7C4255V 7C4265V 7C4275V 7C4285V FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) Configuration CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V ...
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... FIRST LOAD (FL) Figure 2. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration Document #: 38-06012 Rev. *A CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. ...
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... Low-Voltage Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4285V–10ASC 15 CY7C4285V–15ASI 25 CY7C4285V–25ASC Document #: 38-06012 Rev. *A CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Package Package Name Type A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V ...
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... Document Title: CY7C4255V, CY7C4265V, CY7C4275V, CY7C4285V 32K/64K x 18 Low Voltage Deep Sync FIFOs Document Number: 38-06012 Issue REV. ECN NO. Date Change ** 106473 09/10/01 *A 122264 12/26/02 Document #: 38-06012 Rev. *A Orig. of Description of Change SZV Change from Spec number: 38-00654 to 38-06012 RBI Power up requirements added to Maximum Ratings Information ...