CY7C443-30JC Cypress Semiconductor Corporation., CY7C443-30JC Datasheet

no-image

CY7C443-30JC

Manufacturer Part Number
CY7C443-30JC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C443-30JC
Manufacturer:
CY
Quantity:
208
43
Cypress Semiconductor Corporation
Document #: 38-06032 Rev. *A
Features
Functional Description
The CY7C441 and CY7C443 are high-speed, low-power,
first-in first-out (FIFO) memories with clocked read and write
interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a
512 word by 9 bit memory array, while the CY7C443 has a
2048 word by 9 bit memory array. These devices provide so-
• High-speed, low-power, first-in first-out (FIFO)
• 512 x 9 (CY7C441)
• 2,048 x 9 (CY7C443)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
• Low power — I
• Fully asynchronous and simultaneous read and write
• Empty, Almost Empty, and Almost Full status flags
• TTL compatible
• Parity generation/checking
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Center power and ground pins for reduced noise
• Width Expansion Capability
• Available in PLCC packages
Logic Block Diagram
memories
time)
operation
MR
CKW
POINTER
CONTROL
WRITE
RESET
WRITE
LOGIC
LOGIC
CC
ENW
=70 mA
REGISTER
REGISTER
INPUT
OUTPUT
2048x 9
ARRAY
512 x 9
Q
D
RAM
0– 8
0– 8
3901 North First Street
CKR
POINTER
CONTROL
LOGIC
READ
LOGIC
READ
FLAG
C441-1
ENR
lutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
Both FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW). When ENW is asserted, data is written into the
FIFO on the rising edge of the CKW signal. While ENW is held
active, data is continually written into the FIFO on each CKW
cycle. The output port is controlled in a similar manner by a
free-running read clock (CKR) and a read enable pin (ENR).
The read (CKR) and write (CKW) clocks may be tied together
for single-clock operation or the two clocks may be run inde-
pendently for asynchronous read/write applications. Clock fre-
quencies up to 83.3 MHz are acceptable.
The CY7C441 and CY7C443 clocked FIFOs provide two sta-
tus flag pins (F1 and F2). These flags are decoded to deter-
mine one of four states: Empty, Almost Empty, Intermediate,
and Almost Full (Table 1). The flags are synchronous; i.e.,
change state relative to either the read clock (CKR) or the write
clock (CKW). The Empty and Almost Empty states are updat-
ed exclusively by the CKR while Almost Full is updated exclu-
sively by CKW. The synchronous flag architecture guarantees
that the flags maintain their status for some minimum time.
The CY7C441 and the CY7C443 use center power and
ground for reduced noise. Both configurations are fabricated
using an advanced.65 m CMOS technology. Input ESD pro-
tection is greater than 2001V, and latch-up is prevented by
reliable layout techniques and guard rings.
Clocked 512 x 9, 2K x 9 FIFOs
F
F
1
2
San Jose
Pin Configuration
ENW
CKW
V
V
NC
Q
D
CC
F1
F2
SS
0
0
5
6
7
8
9
10
11
12
13
Q
D
14 15 16 17
1
1
4
Q
Top View
D
3 2 1
PLCC
2
2
Q
CA 95134
D
3
7C441
7C443
3
NC
NCD
Revised December 26, 2002
32
Q
1819 20
4
4
31
D
Q
5
5
30
Q
D
29
28
27
26
25
24
23
22
21
6
6
C441-2
D
D
NC
MR
V
CKR
ENR
Q
Q
SS
7
8
8
7
CY7C441
CY7C443
408-943-2600
[+] Feedback

Related parts for CY7C443-30JC

CY7C443-30JC Summary of contents

Page 1

... The CY7C441 and CY7C443 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a 512 word by 9 bit memory array, while the CY7C443 has a 2048 word by 9 bit memory array. These devices provide so- Logic Block Diagram ...

Page 2

... PLCC 32-Pin PLCC Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... > 200 mA Operating Range Range Temperature Commercial +70 C Industrial – +85 C Description CY7C441 CY7C443 7C441–20 7C441–30 7C443–20 7C443– ...

Page 3

... Mil/Ind 150 = Max., Com’ Mil/Ind 80 = Max., Com’ Mil/Ind 30 Test Conditions MHz 5.0V CC 3.0V R2 GND 333 3 ns C441-4 2V CY7C441 CY7C443 7C441–20 7C441–30 7C443–20 7C443–30 2.4 2.4 V 0.4 0.4 0 2 0.8 –0.5 0.8 –0.5 0.8 V +10 –10 +10 – ...

Page 4

... SKEW1 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle SKEW2 CY7C441 CY7C443 7C441–20 7C441–30 7C443–20 7C443–30 Max ...

Page 5

... CKL ENABLED WRITE DISABLED WRITE HEN t t SEN HEN CKR t t CKH CKL ENABLED READ DISABLED READ NEW WORD t HEN t t SEN HEN CY7C441 CY7C443 C441 C441-7 Page [+] Feedback ...

Page 6

... OHMR SKEW1 before R4, R4 includes W1 in the flag update and therefore updates the FIFO to the Almost Empty SKEW2 CY7C441 CY7C443 t MRR t MRR t ...

Page 7

... SKEW2 ENABLED WRITE t FD [17, 18 ENABLED READ t SKEW2 ENABLED WRITE WRITE t FD CY7C441 CY7C443 ENABLED IGNORED READ READ C441 ENABLED ENABLED READ READ C441-11 before R4, R4 includes W3 SKEW2 Page ...

Page 8

... CKW is clock and CKR is opposite clock. 24. Count = 2032 indicates Almost Full for CY7C443 and count = 496 indicates Almost Full for CY7C441. Values for the CY7C441 count are shown in brackets. 25. The dashed lines show W3 as flag update write rather than an enabled write because ENW is deasserted. ...

Page 9

... F1 and F2 being LOW. All data outputs ( LOW at the rising edge of MR. In order for the FIFO 0–8 to reset to its default state, a falling edge must occur on MR and the user must not read or write while MR is LOW (unless CY7C441 CY7C443 2032 2033 [496] [497 ...

Page 10

... For example, if the CY7C443 FIFO contains 2031 words (2032 words or greater indicates Almost Full in the CY7C443), the next write (rising edge of CKW while ENW=LOW) causes the F1 and F2 pins to output the Almost Full state. Table 1. Flag Truth Table ...

Page 11

... The same principles apply for updating the flags when a tran- sition from the Almost Full to the Intermediate state occurs. If the CY7C443 just reaches the Almost Full state (2032 words) and then two words are read, a write clock (CKW) will be re- quired to update the flag to the Intermediate state. If ENW is LOW during the flag update cycle, the count and data update in addition to the flags ...

Page 12

... F2 in FIFO Intermediate Note: 28. Applies to both the CY7C441 and CY7C443 operations. Document #: 38-06032 Rev. *A [28 ] Next State Operation of FIFO F1 Write Empty 0 (ENW = LOW) Write Empty 0 (ENW = LOW) Read AE 1 (ENR = HIGH) Read AE 1 ...

Page 13

... Intermediate 1 1 494 Intermediate 1 1 495 Note: 29. The CY7C441 Almost Full state is represented by 496 or more words. 30. The CY7C443 Almost Full state is represented by 2032 or more words. Ordering Information 512x9 Clocked FIFO Speed Package (ns) Ordering Code Name 12 CY7C441–12JC J65 CY7C441–12JI ...

Page 14

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 32-Lead Plastic Leaded Chip Carrier J65 CY7C441 CY7C443 Page [+] Feedback ...

Page 15

... Document Title: CY7C441 / CY7C443 Clocked 512 FIFOs Document Number: 38-06032 Issue Orig. of REV. ECN NO. Date Change ** 110173 09/29/01 *A 122283 12/26/02 Document #: 38-06032 Rev. *A Description of Change SZV Change from Spec number: 38-00124 to 38-06032 RBI Power up requirements added to Maximum Ratings Information CY7C441 CY7C443 ...

Related keywords