CY7C443-12JI Cypress Semiconductor Corporation., CY7C443-12JI Datasheet

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CY7C443-12JI

Manufacturer Part Number
CY7C443-12JI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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CY7C443-12JI
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CY7C443-12JI
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Cypress Semiconductor Corporation
Document #: 38-06032 Rev. *A
Features
Functional Description
The CY7C441 and CY7C443 are high-speed, low-power,
first-in first-out (FIFO) memories with clocked read and write
interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a
512 word by 9 bit memory array, while the CY7C443 has a
2048 word by 9 bit memory array. These devices provide so-
• High-speed, low-power, first-in first-out (FIFO)
• 512 x 9 (CY7C441)
• 2,048 x 9 (CY7C443)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
• Low power — I
• Fully asynchronous and simultaneous read and write
• Empty, Almost Empty, and Almost Full status flags
• TTL compatible
• Parity generation/checking
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Center power and ground pins for reduced noise
• Width Expansion Capability
• Available in PLCC packages
Logic Block Diagram
memories
time)
operation
MR
CKW
CONTROL
POINTER
WRITE
WRITE
LOGIC
RESET
LOGIC
CC
ENW
=70 mA
REGISTER
REGISTER
INPUT
OUTPUT
2048x 9
512 x 9
ARRAY
Q
D
RAM
0– 8
0– 8
3901 North First Street
CKR
CONTROL
POINTER
LOGIC
READ
LOGIC
FLAG
READ
C441-1
ENR
lutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
Both FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW). When ENW is asserted, data is written into the
FIFO on the rising edge of the CKW signal. While ENW is held
active, data is continually written into the FIFO on each CKW
cycle. The output port is controlled in a similar manner by a
free-running read clock (CKR) and a read enable pin (ENR).
The read (CKR) and write (CKW) clocks may be tied together
for single-clock operation or the two clocks may be run inde-
pendently for asynchronous read/write applications. Clock fre-
quencies up to 83.3 MHz are acceptable.
The CY7C441 and CY7C443 clocked FIFOs provide two sta-
tus flag pins (F1 and F2). These flags are decoded to deter-
mine one of four states: Empty, Almost Empty, Intermediate,
and Almost Full (Table 1). The flags are synchronous; i.e.,
change state relative to either the read clock (CKR) or the write
clock (CKW). The Empty and Almost Empty states are updat-
ed exclusively by the CKR while Almost Full is updated exclu-
sively by CKW. The synchronous flag architecture guarantees
that the flags maintain their status for some minimum time.
The CY7C441 and the CY7C443 use center power and
ground for reduced noise. Both configurations are fabricated
using an advanced.65 m CMOS technology. Input ESD pro-
tection is greater than 2001V, and latch-up is prevented by
reliable layout techniques and guard rings.
Clocked 512 x 9, 2K x 9 FIFOs
F
F
1
2
San Jose
Pin Configuration
ENW
CKW
V
V
NC
D
CC
F1
F2
Q
SS
0
0
5
6
7
8
9
10
11
12
13
Q
D
14 15 16 17
1
1
4
Q
Top View
D
3 2 1
2
PLCC
2
Q
CA 95134
D
3
7C441
7C443
3
NC
NCD
Revised December 26, 2002
32
Q
1819 20
4
4
31
D
Q
5
5
30
Q
D
29
28
27
26
25
24
23
22
21
6
6
C441-2
D
D
NC
MR
V
CKR
ENR
Q
Q
SS
7
8
8
7
CY7C441
CY7C443
408-943-2600

Related parts for CY7C443-12JI

CY7C443-12JI Summary of contents

Page 1

... The CY7C441 and CY7C443 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a 512 word by 9 bit memory array, while the CY7C443 has a 2048 word by 9 bit memory array. These devices provide so- Logic Block Diagram ...

Page 2

... CY7C443 2,048 x 9 32-Pin PLCC Ambient Temperature + – + Page 33 100 110 V CC 10% 10% – ...

Page 3

... Max. 10 ALL INPUT PULSES 90% 90% 10% 10 while data inputs switch MAX ). MAX CY7C441 CY7C443 V 0 0 100 mA 110 Unit C441-5 Page ...

Page 4

... SKEW1 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle SKEW2 CY7C441 CY7C443 7C441–20 7C441–30 7C443–20 7C443–30 Max ...

Page 5

... CKW t t CKH CKL ENABLED WRITE DISABLED WRITE HEN t SEN CKR t t CKH CKL ENABLED READ DISABLED READ HEN t SEN CY7C441 CY7C443 t HEN NEW WORD t HEN Page C441-6 C441-7 ...

Page 6

... FD if the first read shown did not occur or if the read occurred soon enough such that the valid data was OHMR before R4, R4 includes W1 in the flag update and therefore updates the FIFO to the Almost Empty SKEW2 CY7C441 CY7C443 t MRR t MRR t ...

Page 7

... READ READ t t SKEW2 SKEW2 t SKEW2 ENABLED WRITE [17, 18 ENABLED t SKEW2 ENABLED ENABLED WRITE WRITE CY7C441 CY7C443 0 LATENT CYCLE ENABLED IGNORED FLAG READ READ UPDATE READ ENABLED ENABLED READ READ ...

Page 8

... CKW is clock and CKR is opposite clock. 24. Count = 2032 indicates Almost Full for CY7C443 and count = 496 indicates Almost Full for CY7C441. Values for the CY7C441 count are shown in brackets. 25. The dashed lines show W3 as flag update write rather than an enabled write because ENW is deasserted. ...

Page 9

... ENABLED ENABLED ENABLED WRITE WRITE WRITE [17, 23, 24, 27] 2031 2032 [495] [496 ENABLED ENABLED WRITE WRITE CY7C441 CY7C443 C441-13 2033 [497] W7 ENABLED WRITE R7 C441-15 Page ...

Page 10

... For example, if the CY7C443 FIFO contains 2031 words (2032 words or greater indicates Almost Full in the CY7C443), the next write outputs. New data will (rising edge of CKW while ENW=LOW) causes the F1 and F2 pins to output the Almost Full state. ...

Page 11

... The same principles apply for updating the flags when a tran- sition from the Almost Full to the Intermediate state occurs. If the CY7C443 just reaches the Almost Full state (2032 words) and then two words are read, a write clock (CKW) will be re- quired to update the flag to the Intermediate state. If ENW is LOW during the flag update cycle, the count and data update in addition to the flags ...

Page 12

... F2 in FIFO Intermediate Note: 28. Applies to both the CY7C441 and CY7C443 operations. Document #: 38-06032 Rev. *A [28 ] Next State Operation of FIFO F1 Write Empty 0 (ENW = LOW) Write Empty 0 (ENW = LOW) Read AE 1 (ENR = HIGH) Read AE 1 ...

Page 13

... Intermediate 1 1 494 Intermediate 1 1 495 Note: 29. The CY7C441 Almost Full state is represented by 496 or more words. 30. The CY7C443 Almost Full state is represented by 2032 or more words. Ordering Information 512x9 Clocked FIFO Speed (ns) Ordering Code 12 CY7C441–12JC CY7C441–12JI 14 CY7C441–14JC CY7C441–14JI 20 CY7C441– ...

Page 14

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 32-Lead Plastic Leaded Chip Carrier J65 CY7C441 CY7C443 Page ...

Page 15

... Document Title: CY7C441 / CY7C443 Clocked 512 FIFOs Document Number: 38-06032 Issue REV. ECN NO. Date ** 110173 09/29/01 *A 122283 12/26/02 Document #: 38-06032 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00124 to 38-06032 RBI Power up requirements added to Maximum Ratings Information CY7C441 CY7C443 ...

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