SAA6750H NXP Semiconductors, SAA6750H Datasheet
SAA6750H
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SAA6750H Summary of contents
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... DATA SHEET SAA6750H Encoder for MPEG2 image recording (EMPIRE) Product specification Supersedes data of 1998 Sep 07 File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 2000 May 03 ...
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... THERMAL CHARACTERISTICS 10 CHARACTERISTICS 11 APPLICATION INFORMATION 12 PACKAGE OUTLINE 13 SOLDERING 13.1 Introduction to soldering surface mount packages 13.2 Reflow soldering 13.3 Wave soldering 13.4 Manual soldering 13.5 Suitability of surface mount IC packages for wave and reflow soldering methods 14 DATA SHEET STATUS 15 DEFINITIONS 16 DISCLAIMERS 17 PURCHASE OF PHILIPS I2C COMPONENTS 2 Product specification SAA6750H ...
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... The SAA6750H is a stand-alone single chip video encoder performing real time MPEG2 compression of digital video data. The video data input of the SAA6750H accepts a digital YUV video data stream in ITU-T 601 format. PAL standard and 720 pixels by 576 lines, as well as NTSC and 720 pixels by 480 lines, are covered ...
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... For video editing the SAA6750H can be interfaced gluelessly to a video input processor with ITU-T 656 compliant digital video output. In order to link the SAA6750H to the PC, the use of the PCI bridge SAA7146 is recommended. By this bridge the MPEG2 video ES can 2 C-bus before start be transmitted via the PCI-bus to a HardDisc (HD). ...
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... T ambient temperature amb 4 ORDERING INFORMATION TYPE NUMBER NAME SAA6750H SQFP208 2000 May 03 PARAMETER PACKAGE DESCRIPTION plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 28 3.4 mm; high stand-off height 5 Product specification SAA6750H MIN. TYP. MAX. UNIT 3.0 3.3 3.6 V 0.22 0.56 A 0.73 2.0 W 25.6 27.0 28.6 MHz 100 400 kHz 1 ...
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... YUV7 to YUV0 89 FID 90 HSYNC 91 VSYNC 93 CLOCK VCLK 27 MHz GENERATION (27 MHz) SAA6750H 96 RESETN start 97 MAD C-BUS SDA TRANSCEIVER 99 SCL 1, 11, 21, 33, 43, 53, 63, 23, 25, 27, 75, 77, 79, 70, 92, 95, 105, 115, 137, 81, 83, 127, 129, 131, 18 ...
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... DRAM data interface bit 47 ground for pad ring 3 DRAM data interface bit 48 3 DRAM data interface bit 49 3 DRAM data interface bit 50 3 DRAM data interface bit 51 supply voltage for pad ring 3 DRAM data interface bit 52 7 Product specification SAA6750H DESCRIPTION ...
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... Product specification SAA6750H DESCRIPTION ...
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... ASIP port data bit 7; note 2 ground for pad ring 3 ASIP port data bit 8; note 2 3 ASIP port data bit 9; note 2 3 ASIP port data bit 10; note 2 3 ASIP port data bit 11 (MSB); note 2 9 Product specification SAA6750H DESCRIPTION 2 C-bus) C-bus) ...
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... Product specification SAA6750H DESCRIPTION ...
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... DRAM data interface bit 8 3 DRAM data interface bit 9 3 DRAM data interface bit 10 3 DRAM data interface bit 11 ground for pad ring 3 DRAM data interface bit 12 3 DRAM data interface bit 13 11 Product specification SAA6750H DESCRIPTION ...
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... I 1 pin for reset control 7 pins for test purposes 1 pin not connected 1 pin for internal test purposes. Supply (68 pins): 16 core supply pins 18 I/O cell supply pins 16 core ground pins 18 I/O cell ground pins. 12 Product specification SAA6750H DESCRIPTION via a resistor C-bus ...
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... The data transfer between the processing units is carried out via FIFO memories or the external DRAM (see Fig.1). The set of functions of the SAA6750H is determined to a high extent by the microcode of the internal Application Specific Instruction-set Processor (ASIP). Detailed information is given in the software specification. ...
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... RESETN and gets active as soon as RESETN becomes LOW not depending on the external clock signal. The asynchronous reset forces the SAA6750H into reset mode which does directly affect the behaviour of the output and I/O pins (see Table 2). This does guarantee a defined state of the pins even if no clock signal is available ...
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... I C-bus control register are in reset mode. This mode allows e.g. operation of a second device SAA6750H. Therefore output and I/O pins are in input or 3-state mode (see Table 2). The external DRAM will not be refreshed. After setting E_SP back to LOW, the internal reset will remain active for 7562 clock cycles ...
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... See Section 7.3.3 for detailed information about the synchronization signals. The external reference clock VCLK has to be synchronized to the video input data. 16 Product specification SAA6750H SOFT RESET MODE input 3-state 3-state 3-state 3-state 3-state normal operating ...
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... The video front-end and formatter module consists of four submodules: 1. The 8-bit data interface and the related control signals connect the SAA6750H to external data sources such as e.g. Philips SAA711x product family 2. The formatter submodule covers two main functions: the processing of the synchronization information ...
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... C-bus control register words A1, A2 and A3. The valid range + Product specification DESCRIPTION 2( a3 +30 +24 +24 +30 SAA6750H + +13 3 ...
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... Sync processing Because the synchronization information may be delivered by a video data source in two different ways, the internal sync processing of the SAA6750H is carried out in two related modes: 1. The ITU-T 656 mode: The ITU-T 656 recommendation describes the unidirectional interconnection between a video data source and a video data sink ...
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... Fig.4 External sync timing of SAA711x; 50 Hz; lines 308 to 321. 2000 May 03 623 624 625 1 2 (310) (311) (312) (1) (2) 311 312 313 314 315 (311) (312) (313) (1) (2) 20 Product specification SAA6750H (3) (4) (5) (6) (7) 316 317 318 319 320 (3) (4) (5) (6) (7) 8 (8) MHB662 ...
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... SAA711x proprietary timing; note 3 Notes 1. Changes of video standard or synchronization set-up settings are only allowed in init mode or soft reset mode. See Section 7.2.3 for information of the SAA6750H operating modes. 2. See the SAA711x documentation illustrated in Figs 3 and 4. 7.3.3.6 Sync processing NTSC (60 Hz This NTSC (60 Hz) input signal has 525 lines per frame and typically takes 1716 clock cycles per line ...
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... Fig.6 External sync timing of SAA711x; 60 Hz; lines 261 to 274. 2000 May (1) (2) (3) (4) (5) 263 264 265 266 267 (1) (2) (3) ( (6) (7) (8) (9) (10) 268 269 270 271 272 (5) (6) (7) (8) (9) Product specification SAA6750H 11 (11) MHB664 273 274 (10) (11) MHB665 ...
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... SAA711x proprietary timing; note 3 Notes 1. Changes of video standard or synchronization set-up settings are only allowed in init mode or soft reset mode. See Section 7.2.3 for information of the SAA6750H operating modes. 2. See data sheet SAA711x documentation illustrated in Figs 5 and 6. 7.3.3.7 Sync processing coding characteristics according to “ITU-T 656” ...
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... SAV Fig.8 Digital vertical timing (PAL Product specification SAA6750H line line line 311 ( line 336 ( line 624 ( line 625 ( MHB667 H (EAV) H (SAV ...
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... H control signal start of digital active line co-sited co-sited 1440 line line line line 264 ( line 273 ( line 283 ( line 525 ( MHB669 SAA6750H next line MHB668 ...
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... Notes during field during field during field blanking elsewhere SAV EAV. 4. Protection bits are ignored by SAA6750H data processing. 7.4 Macroblock processor 7.4.1 G ENERAL The MacroBlock Processor (MBP) performs the compression of macroblocks. It fetches its input data from the external DRAM memory where this was stored by the video front-end and formatter ...
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... These words are stored into the 4 Mbit output buffer located in the external DRAM. To reduce the memory needs of the compressed macroblock data, a pre-packing to get words of 24 valid bits is performed before storing data for packing. 27 Product specification SAA6750H ...
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... External address decoding External address decoding mode may be appropriate if e.g. an external address decoding hardware is available or if the SAA6750H is the only slave on the bus. The data output port is selected by setting pin CSN to LOW. In this mode, the internal address decoder is disabled and consequently the setting of bytes Bus address is ignored ...
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... RDY The upper watermark reporting may be used by the host to prevent data overflow of the output buffer of the SAA6750H. The fullness of the data output buffer located in the external DRAM is monitored. If the current value is two times or more than two times the value programmed in bytes ‘BS_BUFFER upper level’ in the I register, the signal URQN goes to LOW ...
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... Chapter “Characteristics”). A new transfer cycle may not be started as long as DTACK_RDY is LOW or the SAA6750H is driving the data bus. CSN has to be HIGH all the time. See Fig.16 and Chapter “Characteristics” for timing information. 2. External address decoding The host starts a data transfer cycle by setting the CSN signal to LOW (see Fig ...
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... It is not possible to write data into a register and read it back later on. Due to the internal memory architecture data may only be transmitted to the subaddresses 00H to 03H when the SAA6750H is in init mode. After the control bit E_ST is set 2 to logic 1, sending data via the I 00H to 03H is forbidden. ...
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... The first byte to be received will be the MSB certain information is needed, the read transfer has to be carried out until the specific byte is available. The data transfer has to be closed by the I acknowledge) after the last data byte. This tells the SAA6750H to stop sending further data. The transfer has to follow this scheme: ...
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... ASIP; contents depending on the ASIP software register bank that can be read by the ASIP; used to control the ASIP externally; the function of the register settings is depending on the ASIP software register containing the hardware control bits of the SAA6750H ...
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... SRAM memory containing a constant table for the macroblock processor quantization function. The data to be loaded into this memory will be part of the application software and described in the software specification. Remark: Data may only be sent to this subaddress if the SAA6750H is in the init mode (see Table 23). 7.9.4.4 ...
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... MSB of register 1 will be received next. Consequently, 21 data words have to be read if the data of register 6 is needed. The register data depends on the ASIP’s software and the state of the SAA6750H. A description will be part of the software specification. 2000 May 03 ...
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... May 03 DEPTH WIDTH DESIGN BLOCK (WORDS) (BITS) ASIP 14 2 C-bus to address 00H will always be DEPTH WIDTH DESIGN BLOCK (WORDS) (BITS Product specification SAA6750H DATA TRANSFER MODE 24 random access write mode DATA TRANSFER MODE 160 write mode 2 C-bus ...
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... SH7 SH6 SH5 X X BL5 BU7 BU6 BU5 X BU14 BU13 DADR7 DADR6 DADR5 DADR15 DADR14 DADR13 DADR12 DADR11 DADR10 DADR9 DADR8 37 Product specification SAA6750H BUS E_ST E_SP SMOD PMI4 PMI3 PMI2 WR4 WR3 WR2 RD4 RD3 RD2 BUF4 BUF3 ...
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... FID signal polarity selection; LOW: FID signal not inverted (FID = LOW indicates odd field); HIGH: FID signal inverted (FID = HIGH indicates odd field); this setting takes affect for external as well as for SAV and EAV sync 38 Product specification SAA6750H DESCRIPTION ...
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... Bus address (MSB) to DADR15 Notes 1. Changes of this setting are only allowed in init mode or soft reset mode. See Section 7.2.3 for information of the SAA6750H operating modes. 2. The range of sensible values is 00H to 10H for PAL and 00H to 07H for NTSC. 2000 May 03 DATA NAME ...
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... The engine control bits are used to set the SAA6750H in a specific operating mode. After reset mode the init mode will be activated automatically. For information about the operating modes of the SAA6750H refer to Table 1. 2 7.9.5 I ...
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... Bus address (MSB) 7.10 DRAM interface 7.10.1 G ENERAL The DRAM interface of the SAA6750H schedules and handles all accesses of internal read and write clients to the external 4 4 Mbit DRAM memory. It also takes care of the DRAM refresh after Power-on reset and performs the initialization of the external DRAM. ...
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... SAA6750H is in operating mode (see Table 1). 7.10.3.4 Memory sharing The SAA6750H can be part of a system in which it shares the memory with other devices. To this end the DRAM interface output ports of the SAA6750H can be put to 3-state respectively input state by an appropriate setting of ...
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... Philips Semiconductors Encoder for MPEG2 image recording (EMPIRE) Table 25 Boundary Scan Test (BST) instructions supported by the SAA6750H INSTRUCTION BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO, when no test operation of the component is required. EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections. ...
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... PARAMETER R thermal resistance from junction to th(j-a) ambient 2000 May 03 CONDITIONS MIN. 0.5 note 1 0.5 0 note 2 2000 note 3 200 CONDITIONS in free air; soldered to a PCB with supply and ground plane 44 Product specification SAA6750H MAX. UNIT +4 100 mA 2.0 W +150 +2000 V +200 V ...
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... 3 3 sink current 3 mA load current sink current 3 mA load current DD Product specification SAA6750H MIN. TYP. MAX. 3.0 3.3 3.6 3.0 3.3 3.6 40 180 0.22 0.56 0.73 2.0 0.5 +0.8 2.0 5 0.5 +0.8 2.0 5.5 125 10 10 0.5 +0.8 2.0 5.5 0.4 2 ...
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... IH DD any pin except CASN only CASN pin 3 mA sink current 2 HIGH 0 2 Product specification SAA6750H TYP. MAX. UNIT 0 0 ...
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... note 160 5T 100 Product specification SAA6750H TYP. MAX. UNIT ...
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... May 03 CONDITIONS MIN note 100 0. sink current sink current 0 1.3 0.6 100 0.6 0.6 for all other modes Product specification SAA6750H TYP. MAX. UNIT 400 kHz 0. 5.5 V + ...
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... VCLK data and control inputs data and control outputs 2000 May HIGH t HD;DAT t f(VCLK) t SU;DAT valid not valid t OH;DAT valid not valid Fig.12 Clock data timing. 49 Product specification SAA6750H t LOW t r(VCLK) valid valid MHB671 2.0 V 1.5 V 0.8 V 2.0 V 0.8 V 2.4 V 0.4 V ...
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... RA = row address column address. Fig.13 DRAM fast page mode write cycles to external DRAM. 2000 May CAS ASC t RAH t CAH RA CA1 CA2 DATA1 DATA2 50 Product specification SAA6750H t RHCP t RRH t WCH CA3 CA4 DATA3 DATA4 DATA5 CA5 MHB672 ...
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... May CAS CSS t ASC t RAH t CAH RA CA1 CA2 t CAC t RAC XXXX DATA1 t VCLK t RP Fig.15 DRAM initialization sequence. 51 Product specification SAA6750H t RHCP t RRH t RCH t RDH t CSH CA3 CA4 DATA2 DATA3 DATA4 9 cycles are provided t RP CA5 MHB673 MHB674 ...
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... Product specification SAA6750H second data phase stop read data t idl t dhr t dz second data phase stop read data t dhr idl address MHB675 ...
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... Mbit EXTERNAL DRAM audio clock SAA7112/ SAA6750H SAA7114 MPEG2 VIDEO ENCODER CVBS SAA7185 PCI-bus PCI TO VGA SCSI HARDDISK MONITOR Fig.18 PC application circuit. 53 Product specification SAA6750H SAA7146A PCI BRIDGE ES data DEBI 2 I C-bus MHB677 CPU AND MEMORY ...
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... scale (1) ( 0.27 0.20 28.1 28.1 30.9 0.5 0.17 0.09 27.9 27.9 30.3 REFERENCES JEDEC EIAJ MS-029 detail 30.9 0.75 1.3 0.2 0.08 0.08 30.3 0.45 EUROPEAN PROJECTION Product specification SAA6750H SOT316 (1) ( 1.39 1. 1.11 1.11 0 ISSUE DATE 99-12-27 00-01-25 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 55 Product specification SAA6750H ...
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... This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. 56 Product specification SAA6750H SOLDERING METHOD (1) WAVE REFLOW suitable ...
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... C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 57 Product specification SAA6750H These products are not Philips Semiconductors 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Encoder for MPEG2 image recording (EMPIRE) 2000 May 03 NOTES 58 Product specification SAA6750H ...
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... Philips Semiconductors Encoder for MPEG2 image recording (EMPIRE) 2000 May 03 NOTES 59 Product specification SAA6750H ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...