CY7C63231A Cypress Semiconductor Corporation., CY7C63231A Datasheet
![no-image](/images/manufacturer_photos/0/1/180/cypress_semiconductor_corporation__sml.jpg)
CY7C63231A
Available stocks
Related parts for CY7C63231A
CY7C63231A Summary of contents
Page 1
CY7C63221A/31A enCoRe™ USB Low-speed USB Peripheral Controller Cypress Semiconductor Corporation Document #: 38-08028 Rev. *B • 3901 North First Street • San Jose enCoRe™ USB CY7C63221/31A , CA 95134 • 408-943-2600 Revised Sep 16, 2004 [+] Feedback ...
Page 2
FOR FOR 1.0 FEATURES ..................................................................................................................................... 5 2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6 2.1 enCoRe USB - The New USB Standard .................................................................................... 6 3.0 LOGIC BLOCK DIAGRAM ............................................................................................................. 7 4.0 PIN CONFIGURATIONS ................................................................................................................. 7 5.0 PIN ASSIGNMENTS ....................................................................................................................... 7 6.0 PROGRAMMING MODEL ...
Page 3
FOR FOR 15.0 USB REGULATOR OUTPUT ...................................................................................................... 27 16.0 PS/2 OPERATION ....................................................................................................................... 28 17.0 12-BIT FREE-RUNNING TIMER ................................................................................................. 28 18.0 PROCESSOR STATUS AND CONTROL REGISTER ............................................................... 29 19.0 INTERRUPTS .............................................................................................................................. 31 19.1 Interrupt Vectors .................................................................................................................... 31 19.2 Interrupt Latency .................................................................................................................... ...
Page 4
FOR FOR Figure 8-1. Program Memory Space with Interrupt Vector Table ........................................................ 11 Figure 9-1. Clock Oscillator On-chip Circuit ......................................................................................... 14 Figure 9-2. Clock Configuration Register (Address 0xF8) ................................................................... 14 Figure 10-1. Watchdog Reset (WDR, Address 0x26) .......................................................................... 17 Figure ...
Page 5
FOR FOR 1.0 Features • enCoRe™ USB - enhanced Component Reduction — Internal oscillator eliminates the need for an external crystal or resonator — Interface can auto-configure to operate as PS/2 or USB without the need for external components to ...
Page 6
FOR FOR 2.0 Functional Overview 2.1 enCoRe USB - The New USB Standard Cypress has reinvented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe™ USB—“enhanced Component Reduction.” Cypress has leveraged its design ...
Page 7
... VREG/P2.0 CC XTALIN/P2.1 10 XTALOUT/P2.2 9 CY7C63231A/ CY7C63221A-XC 18-Pin/Pad USB differential data lines (D– and D+), or PS/2 clock and data 12 13 signals (SDATA and SCLK GPIO Port 0 capable of sinking mA/pin, or sinking 15, 16, 17, 18 controlled low or high programmable current. Can also source 2 mA current, provide a resistive pull-up, or serve as a high- impedance input ...
Page 8
... PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts. Document #: 38-08028 Rev. *B CY7C63231A/ CY7C63221A-XC 18-Pin/Pad 9 6-MHz ceramic resonator or external clock input ...
Page 9
FOR FOR The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two. The return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack ...
Page 10
FOR FOR 7.0 Instruction Set Summary Refer to the CYASM Assembler User’s Guide for detailed information on these instructions. Note that conditional jump instructions (i.e. JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no ...
Page 11
FOR FOR 8.0 Memory Organization 8.1 Program Memory Organization After reset 14-bit PC Figure 8-1. Program Memory Space with Interrupt Vector Table Note: 1. The upper 32 bytes of the 3K PROM are reserved. Therefore, user’s program must not over-write ...
Page 12
FOR FOR 8.2 Data Memory Organization The microcontroller provides 96 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below: After reset 8-bit ...
Page 13
FOR FOR 8.3 I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed ...
Page 14
FOR FOR 9.0 Clocking The chip can be clocked from either the internal on-chip clock, or from an oscillator based on an external resonator/crystal, as shown in Figure 9-1. No additional capacitance is included on chip at the XTALIN/OUT pins. ...
Page 15
FOR FOR execution begins from address 0x0000 after this t executes code. See Section 10.1 for more details Disables the LVR circuit Enables the LVR circuit. Bit 2: Precision USB Clocking Enable The Precision USB Clocking ...
Page 16
FOR FOR Start-up times for the external oscillator depend on the resonating device. Ceramic-resonator-based oscillators typically start in less than 100 µs, while crystal-based oscillators take longer, typically ms. Board capacitance should be minimized on the XTALIN ...
Page 17
FOR FOR 10.3 Watchdog Reset (WDR) The Watchdog Timer Reset (WDR) occurs when the internal Watchdog timer rolls over. Writing any value to the write-only Watchdog Reset Register at address 0x26 will clear the timer. The timer will roll over ...
Page 18
FOR FOR Internal Clock saves the external oscillator start-up time and keeps that oscillator off for additional power savings. The external oscillator mode can be activated when desired, similar to operation at power-up. The sequence of events for these modes ...
Page 19
FOR FOR 12.0 General Purpose I/O Ports Ports 0 and 1 provide versatile GPIO pins that can be read or written (the number of pins depends on package type). 2 GPIO Mode Data Internal Out Data Bus ...
Page 20
FOR FOR Bit # 7 6 Bit Name Notes Read/Write - - Reset 0 0 Bit [7:2]: Reserved Bit [1:0]: P1[1: Port Pin is logic HIGH 0 = Port Pin is logic LOW Bit # 7 6 Bit ...
Page 21
FOR FOR Bit # 7 6 Bit Name Read/Write - - Reset 0 0 Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) Bit [7:2]: Reserved Bit [1:0]: P1[1:0] Mode Port Pin Mode 1 is logic HIGH ...
Page 22
FOR FOR Bit # 7 6 Bit Name Reserved Read/Write - - Reset 0 0 Figure 12-8. Port 2 Data Register (Address 0x02) Bit [7:6]: Reserved Bit [5:4]: D+ (SCLK) and D- (SDATA) States The state of the D+ and ...
Page 23
FOR FOR 13.1 USB Enumeration A typical USB enumeration sequence is shown below. In this description, ‘Firmware’ refers to embedded firmware in the controller. 1. The host computer sends a SETUP packet followed by a DATA packet to USB address ...
Page 24
FOR FOR Bit 3: USB Bus Activity The Bus Activity bit is a “sticky” bit that detects any non-idle USB event has occurred on the USB bus. Once set to HIGH by the SIE to indicate the bus activity, this ...
Page 25
FOR FOR 14.0 USB Device The supports one USB Device Address with two endpoints: EP0 and EP1. 14.1 USB Address Register The USB Device Address Register contains a 7-bit USB address and one bit to enable USB communication. This register ...
Page 26
FOR FOR While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data SETUP ...
Page 27
FOR FOR Bit [3:0]: Mode Bit [3:0] The EP1 Mode Bits operate in the same manner as the EP0 Mode Bits (see Section 14.2). 14.4 USB Endpoint Counter Registers There are two Endpoint Counter registers, with identical formats for both ...
Page 28
FOR FOR 16.0 PS/2 Operation The parts are optimized for combination USB or PS/2 devices, through the following features: 1. USB D+ and D– lines can also be used for PS/2 SCLK and SDATA pins, respectively. With USB disabled, these ...
Page 29
FOR FOR Bit # 7 6 Bit Name Read/Write R R Reset 0 0 Figure 17-1. Timer LSB Register (Address 0x24) Bit [7:0]: Timer lower 8 bits Bit # 7 6 Bit Name Reserved Read/Write - - Reset 0 0 ...
Page 30
FOR FOR 1 = There are pending interrupts pending interrupts. Bit 6: Watchdog Reset The Watchdog Timer Reset (WDR) occurs when the internal Watchdog timer rolls over. The timer will roll over and WDR will occur if ...
Page 31
FOR FOR During a Watch Dog Reset, the Processor Status and Control Register is set to 01XX0001, which indicates a Watch Dog Reset (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). 19.0 Interrupts Interrupts can ...
Page 32
FOR FOR 19.2 Interrupt Latency Interrupt latency can be calculated from the following equation: Interrupt Latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction clock cycles for the ...
Page 33
FOR FOR Bit 1: 128-µs Interrupt Enable The 128-µs interrupt is another source of timer interrupt from the free-running timer. The user should disable both timer interrupts (128-µs and 1.024-ms) before going into the suspend mode to avoid possible conflicts ...
Page 34
FOR FOR CLR Enable [0] USB- (Reg 0x20) CLK PS/2 Int CLR Enable [1] (Reg 0x21) EP1 CLK Int CLR Enable [7] (Reg 0x20) Wake-up CLK Int Figure 19-3. Interrupt Controller ...
Page 35
FOR FOR The polarity that triggers an interrupt is controlled independently for each GPIO pin by the GPIO Interrupt Polarity Registers. Figure 19-6 and Figure 19-7 control the interrupt polarity of each GPIO pin. Bit # 7 6 Bit Name ...
Page 36
FOR FOR 20.0 USB Mode Tables The following tables give details on mode setting for the USB Serial Interface Engine (SIE) for both the control endpoint (EP0) and non-control endpoint (EP1). Table 20-1. USB Register Mode Encoding for Control and ...
Page 37
FOR FOR A 'TX 0 Byte' entry in the IN column means that the SIE will transmit a zero byte packet in response to any IN sent to the endpoint. Sending a 0 byte packet is to complete the status ...
Page 38
FOR FOR Table 20-2. Decode table for Table 20-3: “Details of Modes for Differing Traffic Conditions” Properties of incoming Endpoint Mode Encoding packet Token count buffer dval The validity of the received data Received Token (SETUP, ...
Page 39
FOR FOR Table 20-3. Details of Modes for Differing Traffic Conditions End Point Mode Rcved Token Count Buffer Dval SETUP Packet (if accepting) See20-1 SETUP <= 10 data valid See20-1 SETUP > 10 junk x See ...
Page 40
FOR FOR Table 20-3. Details of Modes for Differing Traffic Conditions(continued token count buffer dval OUT x UC invalid Status OUT Only 0 0 ...
Page 41
FOR FOR 21.0 Register Summary Address Register Name Bit 7 0x00 Port 0 Data 0x01 Port 1 Data 0x02 Port 2 Data Reserved 0x0A GPIO Port 0 Mode 0 0x0B GPIO Port 0 Mode 1 0x0C GPIO Port 1 Mode ...
Page 42
FOR FOR 22.0 Absolute Maximum Ratings Storage Temperature ..........................................................................................................................................–65°C to +150°C Ambient Temperature with Power Applied ...............................................................................................................–0°C to +70°C Supply voltage on V relative to V .................................................................................................................... –0.5V to +7. Input Voltage........................................................................................................................................... –0. Voltage ...
Page 43
FOR FOR Parameter V Differential Input Sensitivity DI V Differential Input Common Mode Range CM V Single Ended Receiver Threshold SE C Transceiver Capacitance IN I Hi-Z State Data Line Leakage LO R External Bus Pull-up resistance (D– ...
Page 44
FOR FOR 24.0 Switching Characteristics Parameter Description Internal Clock Mode F Internal Clock Frequency ICLK F Internal Clock Frequency, USB ICLK2 mode External Oscillator Mode T Input Clock Cycle Time CYC T Clock HIGH Time CH T Clock LOW Time ...
Page 45
FOR FOR . CLOCK crs 10 D− T PERIOD Differential Data Lines Document #: 38-08028 Rev CYC Figure 24-1. Clock Timing 90% 90% 10% ...
Page 46
FOR FOR T PERIOD Crossover Point Differential Data Lines Diff. Data Figure 24-4. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines Document #: 38-08028 Rev. *B Crossover Point Extended SE0 Skew ...
Page 47
... FOR FOR 25.0 Ordering Information EPROM Ordering Code Size CY7C63221A-PXC 3 KB CY7C63221A- CY7C63231A-SXC 3 KB CY7C63231A- CY7C63231A-PXC 3 KB CY7C63231A- CY7C63221A- CY7C63221A-XWC 3 KB 26.0 Package Diagrams Document #: 38-08028 Rev. *B Package Name Package Type P1 16-Pin (300-Mil) PDIP Lead-free P1 16-Pin (300-Mil) PDIP S1 18-Pin Small Outline Package Lead-free ...
Page 48
FOR FOR Die Step: 2031.0 x 2279.0 microns Pad Size microns Document #: 38-08028 Rev. *B 18-Lead (300-Mil) Molded SOIC S1 18-Lead (300-Mil) Molded DIP P3 DIE FORM Cypress Logo (0, ...
Page 49
... P0.5 18 P0.4 enCoRe is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-08028 Rev. *B © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...
Page 50
FOR FOR Document History Page Document Title: CY7C63221/31A enCoRe™ Low-speed USB Peripheral Controller Document Number: 38-08028 Issue REV. ECN NO. Date Change ** 116226 06/17/02 *A 116976 10/23/02 *B 270731 See ECN Document #: 38-08028 Rev. *B Orig. of Description ...