CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet
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CY7C63923-PVXC
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CY7C63923-PVXC Summary of contents
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... I/O pins — 4 I/O pins with 3.3V logic levels Cypress Semiconductor Corporation Document 38-08035 Rev. *E Low-Speed USB Peripheral Controller — Each 3.3V pin supports high-impedance input, internal pull-up, open drain output or traditional CMOS output • ...
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Introduction Cypress has reinvented its leadership position in the low- speed USB market with a new family of innovative microcon- trollers. Introducing enCoRe II USB — “enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to ...
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Logic Block Diagram Low-Speed USB/PS2 3.3V Transceiver Regulator and Pull-up Internal 24 MHz Oscillator Clock Control Crystal Oscillator POR / Low-Voltage Detect Figure 4-1. CY7C633xx/CY7C638xx/CY7C639xx Block Diagram Document 38-08035 Rev. *E Low-Speed Interrupt 4 3VIO/SPI 16 Extended USB SIE ...
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Packages/Pinouts CY7C63801 16-pin PDIP CY7C63310 16-pin PDIP P1.2 SSEL/P1 SCLK/P1 P1.1/D– SMOSI/P1 P1.0/D+ SMISO/P1 P0.6/TIO1 P0.0 P0.5/TIO0 10 7 P0.1 INT2/P0 ...
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... P4.2 43 P4.3 34 P3.0 35 P3.1 36 P3.2 37 P3.3 38 P3.4 39 P3.5 40 P3.6 41 P3.7 15 P2.0 14 P2.1 13 P2.2 12 P2.3 11 P2.4 10 P2.5 9 P2.6 8 P2.7 CY7C63310 CY7C638xx CY7C639xx CY7C63923-XC DIE P4 P3.6 9 P2.6 39 P3.5 10 P2.5 38 P3.4 11 P2.4 37 P3.3 P2 P3.2 P2.2 35 P3.1 34 P3.0 33 P1.7 32 P1.6/SMISO 14 P2.1 31 P1.5/SMOSI P2.0 ...
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Table 5-1. Pin Assignments (continued SSOP PDIP SSOP QSOP SOIC PDIP ...
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Table 5-1. Pin Assignments (continued SSOP PDIP SSOP QSOP SOIC PDIP 45,46 47, – – – ...
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CPU Registers 7.1 Flags Register The Flags Register can only be set or reset with logical instruction. Table 7-1. CPU Flags Register (CPU_F) [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 Bit [7:5]: Reserved ...
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Stack Pointer Register Table 7-4. CPU Stack Pointer Register (CPU_SP) Bit # 7 6 Field Read/Write – – Default 0 0 Bit [7:0]: Stack Pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack 7.1.4 CPU Program ...
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Table 7-8. Source Direct Opcode Instruction Source Address Examples ADD A, [7] ;In this case, the ;value in ;the RAM memory location at ;address 7 is added with the ;Accumulator, and the result ;is placed in the Accumulator. MOV X, ...
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Examples ADD [7], 5 ;In this case, value in the mem- ;ory location at address 7 is ;added to the immediate value of ;5, and the result is placed in ;the memory location at address 7. MOV REG[8], 6 ;In ...
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Instruction Set Summary The instruction set is summarized in Table 8-1 by numerically and serves as a quick reference. If more information is Table 8-1. Instruction Set Summary Sorted Numerically by Opcode Order Instruction Format Flags ...
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Memory Organization 9.1 Flash Program Memory Organization after reset 16-bit PC Figure 9-1. Program Memory Space with Interrupt Vector Table Document 38-08035 Rev. *E Address 0x0000 Program execution begins here after a reset 0x0004 POR/LVD 0x0008 INT0 0x000C SPI ...
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Data Memory Organization The CY7C633xx/638xx/639xx microcontrollers provide up to 256 bytes of data RAM. In normal usage, the SRAM is parti- tioned into two areas: stack, and user variables: after reset 8-bit PSP Top of RAM Memory 9.3 Flash ...
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Two important variables that are used for all functions are KEY1 and KEY2. These variables are used to help discrim- inate between valid SSCs and inadvertent SSCs. KEY1 must always have a value of 3Ah, while KEY2 must have the ...
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The SRAM address of the first of the 64 bytes to be stored in Flash must be indicated using the POINTER variable in the parameter block (SRAM address FBh). Finally, the CLOCK and DELAY value must be set correctly. The ...
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The bulk program is followed by a second erase that leaves the Flash macro in a state ready for writing. The erase, program, erase sequence is then performed on the next lowest Flash ...
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The Internal 32-KHz Low-power Oscillator accuracy ranges from –85% to +120% (between 0°–70° C). For applications that require a higher clock accuracy, the CY7C639xx part can optionally be sourced from an external crystal oscillator. When operating in USB mode, the ...
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External Clock Trim Table 10-2. XOSC Trim (XOSCTR) [0x35] [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 This register is used to calibrate the external crystal oscillator. The reset value is undefined but during ...
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CPU/USB Clock Configuration Table 10-4. CPU/USB Clock Config CPUCLKCR) [0x30] [R/W] Bit # 7 6 Field Reserved USB CLK /2 Disable Read/Write – R/W Default 0 0 Bit 7: Reserved Bit 6: USB CLK/2 Disable This bit only affects ...
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OSC_CR0 Clock Configuration Table 10-5. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 Bit [7:6]: Reserved Bit 5: No Buzz During sleep (the Sleep bit is set in the ...
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USB Oscillator Lock Configuration Table 10-6. USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W] Bit # 7 6 Field Read/Write – – Default 0 0 This register is used to trim the Internal 24-MHz Oscillator using received low-speed USB packets ...
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Clock In / Clock Out Configuration Table 10-8. Clock I/O Config (CLKIOCR) [0x32] [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 Bit [7:5]: Reserved Bit 4: XOSC Select This bit when set, selects the ...
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Table 11-1. System Status and Control Register (CPU_SCR) [0xFF] [R/W] Bit # 7 6 Field GIES Reserved Read/Write R – Default 0 0 The bits of the CPU_SCR register are used to convey status and control of events for various ...
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Table 11-2. Reset Watchdog Timer (RESWDT) [0xE3] [W] Bit # 7 6 Field Read/Write W W Default 0 0 Any write to this register will clear Watchdog Timer, a write of 0x38 will also clear the Sleep Timer Bit [7:0]: ...
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Low-voltage Detect Control Table 13-1. Low-voltage Control Register (LVDCR) [0x1E3] [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 This register controls the configuration of the Power-on Reset / Low-voltage Detection block Bit [7:6]: Reserved ...
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ECO Trim Register Table 13-3. ECO (ECO_TR) [0x1EB] [R/W] Bit # 7 6 Field Sleep Duty Cycle [1:0] Read/Write R/W R/W Default 0 0 This register controls the ratios (in numbers of 32-KHz clock periods) of “on” time versus ...
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P1 Data Table 14-2. P1 Data Register (P1DATA) [0x01] [R/W] Bit # 7 6 Field P1.7 P1.6/SMISO Read/Write R/W R/W Default 0 0 This register contains the data for Port 1. Writing to this register sets the bit values ...
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P4 Data Table 14-5. P4 Data Register (P4DATA) [0x04] [R/W] Bit # 7 6 Field Read/Write R R Default 0 0 This register contains the data for Port 4. Writing to this register sets the bit values to be ...
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Drive (On Designated Pins Only) Pull-Up Enable Output Enable Open Drain Port Data High Sink Data In TTL Threshold 14.2.10 P0.0/CLKIN Configuration Table 14-6. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W] Bit # 7 6 Field Reserved Int Enable Read/Write -- ...
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P0.2/INT0 – P0.4/INT2 Configuration Table 14-8. P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 These registers control the operation of pins P0.2–P0.4 respectively. These pins are shared between the P0.2–P0.4 ...
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P1.0/D+ Configuration Table 14-11. P1.0/D+ Configuration (P10CR) [0x0D] [R/W] Bit # 7 6 Field Reserved Int Enable Read/Write R/W R/W Default 0 0 This register controls the operation of the P1.0 (D+) pin when the USB interface is not ...
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P1.4 – P1.6 Configuration (SCLK, SMOSI, SMISO) Table 14-15. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W] Bit # 7 6 Field SPI Use Int Enable Read/Write R/W R/W Default 0 0 These registers control the operation of pins P1.4–P1.6, respectively. These ...
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Table 14-18. P3 Configuration (P3CR) [0x16] [R/W] (continued) This register exists in CY7C638xx and CY7C639xx. In CY7C638xx this register controls the operation of pins P3.0–P3.1. In the CY7C639xx, this register controls the operation of pins P3.0–P3.7 The 50-mA sink drive ...
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SPI Configure Register Table 15-2. SPI Configure Register (SPICR) [0x3D] [R/W] Bit # 7 6 Field Swap LSB First Read/Write R/W R/W Default 0 0 Bit 7: Swap 0 = Swap function disabled 1 = The SPI block swaps ...
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Table 15-3. SPI Mode Timing vs. LSB First, CPOL and CPHA LSB First CPHA CPOL ...
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Table 15-4. SPI SCLK Frequency SCLK Frequency when CPUCLK = SCLK CPUCLK Select Divisor 12 MHz MHz MHz 10 48 250 KHz 11 96 125 KHz 15.3 SPI Interface Pins The SPI interface uses ...
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Capture 1 Rising Table 16-4. Timer Capture 1 Rising (TCAP1R) [0x23] [R/W] Bit # 7 6 Field Read/Write R/W R/W Default 0 0 Bit [7:0]: Capture 1 Rising [7:0] This register holds the value of the Free-running Timer when ...
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Programmable Interval High Byte Table 16-8. Programmable Interval Timer High (PITMRH) [0x27] [R/W] Bit # 7 6 Field Read/Write – – Default 0 0 Bit [7:4]: Reserved Bit [3:0]: Prog Internal Timer [11:8] This register holds the high-order nibble ...
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Timer Configuration Table 16-11. Timer Configuration (TMRCR) [0x2A] [R/W] Bit # 7 6 Field First Edge Hold Read/Write R/W R/W Default 0 0 Bit 7: First Edge Hold The First Edge Hold function applies to all four capture timers. ...
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Capture Interrupt Status Table 16-13. Capture Interrupt Status (TCAPINTS) [0x2C] [R/W] Bit # 7 6 Field Read/Write – – Default 0 0 Bit [7:4]: Reserved Bit 3: Cap1 Fall Active event falling edge ...
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Interrupt Taken or INT_CLRx Write Interrupt Source (Timer, GPIO, etc.) 17.2 Interrupt Processing The sequence of events that occur during interrupt processing is as follows interrupt becomes active, either because: a. The interrupt condition ...
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Table 17-2. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W] Bit # 7 6 Field GPIO Port 1 Sleep Timer Read/Write R/W R/W Default 0 0 When reading this register There’s no posted interrupt for the corresponding hardware 1 = ...
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Table 17-5. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W] Bit # 7 6 Field ENSWINT Read/Write R/W – Default 0 0 Bit 7: Enable Software Interrupt (ENSWINT) 0= Disable. Writing INT_CLRx register, when ENSWINT is cleared, will cause ...
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Table 17-7. Interrupt Mask 1 (INT_MSK1) [0xE0] [R/W] Bit # 7 6 Field TCAP0 Prog Interval Int Enable Timer Int Enable Read/Write R/W R/W Default 0 0 Bit 7: TCAP0 Interrupt Enable 0 = Mask TCAP0 interrupt 1 = Unmask ...
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Interrupt Vector Clear Register Table 17-9. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W] Bit # 7 6 Field Read/Write R/W R/W Default 0 0 The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending ...
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USB Regulator Output 19.1 VREG Control Table 19-1. VREG Control Register (VREGCR) [0x73] [R/W] Bit # 7 6 Field Read/Write – – Default 0 0 Bit [7:2]: Reserved Bit 1: Keep Alive Keep Alive when set allows the voltage ...
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USB Device 21.1 USB Device Address Table 21-1. USB Device Address (USBCR) [0x40] [R/W] Bit # 7 6 Field USB Enable Read/Write R/W R/W Default 0 0 The content of this register is cleared when a USB Bus Reset ...
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Endpoint 0 Mode Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers the SIE provides an interlocking mechanism to prevent accidental overwriting of data. Table 21-3. Endpoint 0 Mode (EP0MODE) ...
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Endpoint 1 and 2 Mode Table 21-4. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W] Bit # 7 6 Field Stall Reserved Read/Write R/W R/W Default 0 0 Bit 7: Stall When this bit is set ...
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USB Mode Tables Mode Encoding DISABLE 0000 NAK IN/OUT 0001 STATUS OUT ONLY 0010 STALL IN/OUT 0011 STATUS IN ONLY 0110 ACK OUT – STATUS 1011 IN ACK IN – STATUS 1111 OUT NAK OUT 1000 ACK OUT (STALL ...
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Details of Mode for Differing Traffic Conditions Control Endpoint SIE Bus Event Mode Token Count Dval D0/1 DISABLED 0000 STALL_IN_OUT 0011 SETUP > 0011 SETUP <=10 invalid x 0011 SETUP <=10 valid x ...
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Details of Mode for Differing Traffic Conditions 1011 OUT > 1011 OUT <=10 invalid x 1011 OUT <=10 valid x STATUS_IN 0110 SETUP > 0110 SETUP <=10 invalid x 0110 SETUP <=10 valid x 0110 ...
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Register Summary Addr Name P0DATA P0.7 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 01 P1DATA P1.7 P1.6/SMI SO 02 P2DATA 03 P3DATA 04 P4DATA 05 P00CR Reserved Int Enable 06 P01CR CLK Int Output Enable 07–09 P02CR– Reserved Reserved P04CR ...
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Register Summary (continued) Addr Name OSCLCKCR 3C SPIDATA 3D SPICR Swap LSB First 40 USBCR USB Enable 41 EP0CNT Data Data Valid Toggle 42 EP1CNT Data Data Valid Toggle 43 EP2CNT Data Data Valid Toggle 44 ...
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Absolute Maximum Ratings Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied ..... –0°C to +70°C Supply Voltage on V Relative Input Voltage.................................–0. Voltage Applied to Outputs in High-Z ...
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DC Characteristics (continued) Description Parameter General General Purpose I/O Interface R Pull-up Resistance UP V Input Threshold Voltage Low, CMOS ICR mode V Input Threshold Voltage Low, CMOS ICF mode V Input Hysteresis Voltage, CMOS Mode High to low ...
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AC Characteristics (continued) Parameter Description Non-USB Mode Driver Characteristics T SDATA/SCK Transition Fall Time FPS2 SPI Timing T SPI Master Clock Rate SMCK T SPI Slave Clock Rate SSCK T SPI Clock High Time SCKH T SPI Clock Low ...
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T PERIOD Differential Data Lines T PERIOD Differential Data Lines Figure 27-4. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines Document 38-08035 Rev Consecutive Transitions ...
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SS SCK (CPOL=0) T SCKH SCK (CPOL=1) T MDO MOSI MISO SSS SCK (CPOL=0) T SCKH SCK (CPOL=1) MOSI T SDO MISO Document 38-08035 Rev. *E (SS is under firmware control in SPI Master mode) T SCKL ...
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SS SCK (CPOL=0) T SCKH SCK (CPOL=1) T MDO1 MOSI MSB MSB MISO T T MHD MSU SS T SSS SCK (CPOL=0) T SCKH SCK (CPOL=1) MSB MOSI T T SSU SHD T SDO1 MISO MSB Document 38-08035 Rev. *E ...
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... Ordering Information Ordering Code CY7C63923-PVXC CY7C63913-PXC CY7C63903-PVXC CY7C63923-XWC CY7C63823-PXC CY7C63823-SXC CY7C63823-QXC CY7C63813-PXC CY7C63813-SXC CY7C63803-SXC CY7C63801-PXC CY7C63801-SXC CY7C63310-PXC CY7C63310-SXC 29.0 Package Diagrams Document 38-08035 Rev. *E FLASH Size RAM Size 8K 256 48-SSOP 8K 256 40-PDIP 8K 256 28-SSOP 8K 256 Die 8K 256 24-PDIP 8K 256 24-SOIC ...
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Package Diagrams (continued) 16 Lead (150 Mil) SOIC 8 9 0.386[9.804] 0.393[9.982] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] Document 38-08035 Rev. *E 16-Lead (150-Mil) SOIC S16.15 PIN DIMENSIONS IN INCHES[MM] MIN. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms 0.150[3.810] ...
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Package Diagrams (continued) 18 Lead (300 Mil) SOIC - 0.447[11.353] 0.463[11.760] 0.050[1.270] TYP. 0.013[0.330] 0.019[0.482] 24 Lead (300 Mil) SOIC - S13 12 13 0.597[15.163] 0.615[15.621] 0.050[1.270] TYP. 0.013[0.330] 0.019[0.482] Document 38-08035 Rev. *E 18-Lead (300-Mil) ...
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Package Diagrams (continued) 0.033 REF. 12 0.150 0.157 0.228 0.244 13 SEATING PLANE 0.053 0.069 0.004 0.004 0.010 Document 38-08035 Rev Lead (300 Mil) PDIP–P13 24-lead QSOP O241 PIN 0.337 0.344 0.007 0.010 ...
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Package Diagrams (continued) 28-Lead (5.3 mm) Shrunk Small Outline Package O28 Document 38-08035 Rev. *E 40-Lead (600-Mil) Molded DIP P17 CY7C63310 CY7C638xx CY7C639xx 51-85079-*C 51-85019-*A Page ...
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... Document 38-08035 Rev. *E © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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Document History Page Document Title: CY7C63310/CY7C638xx/CY7C639xx enCoRe II Low-Speed USB Peripheral Controller Document Number: 38-08035 Orig. of Rev. ECN No. Issue Date Change ** 131323 12/11/03 *A 221881 See ECN *B 271232 See ECN *C 299179 See ECN *D 322053 ...