MCVVQ111AFB Freescale Semiconductor, Inc, MCVVQ111AFB Datasheet
MCVVQ111AFB
Related parts for MCVVQ111AFB
MCVVQ111AFB Summary of contents
Page 1
... LCD panel. Horizontal and vertical sync outputs are provided. The MCVVQ111AFB is designed to operate under two input voltages: one is from 2.7 to 5.5 volts ,and the other is 11 volts, A Sleep mode can be set to reduce power consumption. ...
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... VIDEO RESTORE 0. CLAMP 100n Blkg OSD Level Detect 3 OSD In White 12 AGND Test Mode 41 GAIN MCVVQ111AFB Figure 1 Block Diagram 11V 0.1u 10u 100n VOLTAGE REGULATOR PDR TIMING GENERATOR VIDEO AMPS BLK LEVEL & GAIN ADJ. BLK GAMMA BIAS LVL. Ref Gnd ...
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... Supply Current into VBat(Pin 43 and Pin 44), Sleep Mode Pins 13-27 open, Pin 1 = Low, VBat=3.3Volts Supply Current into VDDH Power Consumption, VBat=5.0v VDDH= 11.0v DISPLAY OUTPUT VOLTAGES (voltages referenced to VSS) VDD (source 1.4mA) VEE (sink 1mA) VCOM (source 2mA) MCVVQ111AFB Symbol Value VBat -0.5,+6.0 VDDH 13 T +150 ...
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... IRE video input level, measure VIDL output amplitude with respect to black level, external VDDH at 11V) Black Level Control Range (pin30<BLK LVL> set at 2 volt measure VIDL output black level voltage. MCVVQ111AFB o ( All parameters are specified at Ta=25 C, Pin 1 = High unless noted ...
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... Note: Gain, GAMMA-BIAS & BLACK LEVEL are interrelated control, control range may be different at different combination of those setting. TIMING CHARACTERISTICS (Ta=+25 Note: MCVVQ111AFB is design to work in conjunction with CyberDisplay 320 Monochrome Display, all timing output are expected to fulfill the minimum timing requirement stated at CyberDisplay 320 Monochrome specification table 2-5, revision “2/13, 1998 standard video mode NTSC/PAL ...
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... RENO 27 VIDL 28 VIDLC 29 VIDHC 30 Black Level 31 N/C MCVVQ111AFB Min Typ - 10 Description Logic level input. A logic low sets the IC into the sleep mode. Internal 500K pull- down provided. Used for HODL selection. Logic 1: column inversion output on HODL for ABNORMAL video (such as cue/review/pause mode) ...
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... VSync Sel 48 Ref Gnd. MCVVQ111AFB Description Connect the decoupling capacitor (0.1uF) for VDD Output of the bandgap reference. External capacitor may be required. Not connected For test only. Output indicating the video horizontal freq is within the PLL pull-in range. If PLL is not locked, OK will be set to HIGH. ...
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... Figure 2-Black Level Adjustment 10.0 8.0 6.0 4.0 2 Figure 3 - Gain Adjustment (For 1 Volt video input, Gamma bias was adjusted for a linear characteristic) Gain Control Voltage at Pin 8 (Volt DC) MCVVQ111AFB VIDH VIDL 2.0 Black Level Set Voltage @Pin 30(Volts DC) 3.0 MOTOROLA Jan. 2002 REV 0 Page 8 ...
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... BLACK LVL 4us 2us CLAMP (Internal) VIDEO INPUT @PIN 5 VSYNC OUT @PIN 46 Field 2 VIDEO INPUT @PIN 5 VSYNC OUT @Pin 46 Field 1 MCVVQ111AFB Figure 4 - Horizontal Sync Timing 1/2 Fh Figure 5 - VSync Output Line 1 49 Lines 3.1 mSec Field 1 49 Lines 3.1 mSec Field 2 MOTOROLA Jan. 2002 REV 0 Page 9 ...
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... MCVVQ111AFB Figure 6 - LCD Panel Supply Voltages R 9.0V R 0.3V R BANDGAP SOURCE 2.0V Figure 7 - Video Display vs. Video Input VIDEO INPUT ta VIDEO OUTPUT VIDEO 1/Fh HCK INPUT 525/60 63.5uS 6.05 MHz 625/50 6 MHz 64uS VDDH(11V) 40 VDD(9V) 20 VDDH VCOM(5.8V VDDH VEE(2V VBAT (2.7~5. VREF 22 (VBAT/2) R VSS 21 Video Content Video Display ...
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... MCVVQ111AFB Figure 8 - LCD Panel Vertical & Horizontal Timing VSync Pin 46 t1 VPL Pin VCK Pin HPL t4 Pin 23 HODL Pin 17 HCK Pin 24 t5 Figure 9 - LCD Panel Active Video Timing VCK Pin 15 HPL Pin RENE Pin 25 RENO Pin 26 Cycle time = 1 Field ...
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... Figure 11 - OSD Input Signal Waveform OSD Input Signal Figure 12 - OSD Display Example Row 1 Row 2 Row 3 OSD INPUT For Row 1 OSD INPUT For Row 2 OSD INPUT For Row 3 MCVVQ111AFB Line 258 White Level White Threshold Black Level OSD Threshold Field 2 Line 282 GND GND GND ...
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... All timing values are multiples of the HCK period. The eight timing signals to the CyberDisplay320 LCD display panel are (refer Figures 8-10): •PDR (pin 13) - Power Down Reset is high for normal operation set low when the MCVVQ111AFB is set to the Sleep mode. •VCK (pin 15) - Vertical Clock. The active low output appears every other line, indicating the beginning of an even numbered row present for video lines 22 through 260 only. • ...
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... Only if both of the above conditions meet, the display panel will be enabled. The PDR scheme can be either scheme 1 or scheme 2 depending on the setting of SEL_PDR(pin 42). The difference between these two schemes is: When PDR is asserted during VBlanking, 3 RENE/RENO pulses will be generated under scheme 2 but no RENE/RENO pulse will be generated under scheme 1. MCVVQ111AFB PAL NTSC ...
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... CLAMP 100n Blkg OSD Level OSD Detect 3 White Generator 12 AGND 41 Test Mode GAIN VCOM PIN 18 36K 20K 10K MCVVQ111AFB Figure 13 Application Circuit 11V 10u 100n 0.1u VOLTAGE CONVERTER PDR TIMING GENERATOR 384Fh Q D VIDEO AMPS BLK LEVEL & GAIN ADJ. GAMMA BLK BIAS LVL ...
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... APPLICATION INFORMATION Figure 13 shows the basic application circuit using MCVVQ111AFB along with CyberDisplay320 LCD Panel. Applicable points are: •The components at pins 6, 7, and 9 must neat, tight arrangement connected directly to the ground at pin 4. •It is recommended that a socket NOT be used for the MCVVQ111AFB. ...
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... Figure 15 Gain = 1.5V, Gamma=1V With a smaller gain, the slope in Figure 15 is less steeper than the one in Figure 14 Figure 16 Gain = 1.5V, Gamma = 0.75V With a smaller gamma, the black region turning point in Figure 16 is lower than the one in Figure 14 MCVVQ111AFB MOTOROLA Jan. 2002 REV 0 Page 17 ...
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... USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 Mfax‰: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com MCVVQ111AFB JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, 2 Dai King Street, Taipo Industrial Estate, Tai Po, N ...