PCKV857A NXP Semiconductors, PCKV857A Datasheet

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PCKV857A

Manufacturer Part Number
PCKV857A
Description
Manufacturer
NXP Semiconductors
Datasheet

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PCKV857ADGG
Manufacturer:
PHILIPS
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PCKV857ADGG
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PCKV857ADGV
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Philips
Semiconductors
Product data
Supersedes data of 2002 Dec 13
PCKV857A
100-250 MHz differential
1:10 clock driver
INTEGRATED CIRCUITS
2003 Jul 31

Related parts for PCKV857A

PCKV857A Summary of contents

Page 1

... PCKV857A 100-250 MHz differential 1:10 clock driver Product data Supersedes data of 2002 Dec 13 Philips Semiconductors INTEGRATED CIRCUITS 2003 Jul 31 ...

Page 2

... The PCKV857A is a high-performance, low-skew, low-jitter zero delay buffer designed for 2 and 2 differential data input and output levels. The PCKV857A is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs ( ...

Page 3

... OUT OUT SW00692 3 Product data PCKV857A DESCRIPTION SSTL_2 ground pins SSTL_2 differential outputs SSTL_2 power pins SSTL_2 differential inputs Analog power Analog ground Power-down control input PLL ON/OFF FB FB OUT OUT ...

Page 4

... IN IN PWRDWN −0.3 Note 2 CLK, FB Note 3 0.36 IN CLK, FB Note 3 IN Note 4 V DDQ Note 4 V DDQ and is the voltage at which the differential signals must be crossing Product data PCKV857A LIMITS MIN MAX 0.5 3.6 0.5 3.6 + 0.5 -0.5 V DDQ + 0.5 -0.5 V DDQ ±50 — ±50 — ±50 — ±100 — ...

Page 5

... MHz to 190 MHz MHz to 190 MHz 2 GND DDQ and is the voltage at which the differential signals must be crossing. DDQ PARAMETER 5 Product data PCKV857A LIMITS UNIT MIN TYP MAX −1.2 — — − 0.1 V — — DDQ 1.7 — — — — ...

Page 6

... PCKV857A or or SSTV16857 SSTV16857 The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation 6 Product data PCKV857A LIMITS UNIT MIN TYP MAX -350 0 350 ps — ...

Page 7

... Jul 31 t (O)n Σ (O large number of samples) (O) N Figure 1. Static phase offset t sk(O) Figure 2. Output skew 80 SLR(I) SLR(O) SLR(I) SLR(O) Figure 3. Input and output slew rates 7 Product data PCKV857A t (O SW00882 SW00883 80 20% SW00886 ...

Page 8

... JIT(CC) cycle n cycle n+1 Figure 5. Cycle-to-cycle jitter t t half period n half period JIT(HPER) half period n 2*f O Figure 6. Half-period jitter skew ANY TWO OUTPUTS Figure 7. Skew between any two outputs. 8 Product data PCKV857A SW00884 SW00881 SW00885 SW00396 ...

Page 9

... Figure 8. Duty cycle limits and measurement - Ω Ω Ω Ω Ω Ω Figure 9. Output load test circuit 9 Product data PCKV857A SW00397 SCOPE Ω Ω NOTE GND TT SW00946 ...

Page 10

... Philips Semiconductors 100-250 MHz differential 1:10 clock driver TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2003 Jul 31 10 Product data PCKV857A SOT362-1 ...

Page 11

... Philips Semiconductors 100-250 MHz differential 1:10 clock driver TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm 2003 Jul 31 11 Product data PCKV857A SOT480-1 ...

Page 12

... Product data (9397 750 11759); ECN 853-2394 30057 dated 18 June 2003. Supersedes data of 2002 Decemaber 13 (9397 750 10867). Modifications: • _1 20021213 Product data (9397 750 10867); ECN 853-2394 29181 of 13 December 2002. 2003 Jul 31 Minor changes or corrections to existing product specifications. 12 Product data PCKV857A ...

Page 13

... Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Fax: + 24825 Document order number: 13 Product data PCKV857A  Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 07-03 9397 750 11759 ...

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