HFA3841CN96 Intersil Corporation, HFA3841CN96 Datasheet
HFA3841CN96
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HFA3841CN96 Summary of contents
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... TEMP. RANGE o NUMBER ( HFA3841CN HFA3841CN96 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Microsoft® and Windows® are registered trademarks of Microsoft Corporation. | Intersil and Design is a trademark of Intersil Corporation. PRISM® registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. ...
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Pinout HINPACK- 103 104 HWAIT- 105 V _IO5 CC 106 HA0 107 HA1 108 HA2 109 HA3 110 HA4 111 HA5 112 HA6 113 HA7 114 HIREQ- 115 V _IO3 SS 116 HWE- 117 HA8 118 HA9 HIOWR- 119 HIORD- ...
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HFA3841 Pin Descriptions Host Interface Pins PIN NAME PIN NUMBER HA0-9 106-113, 117, 118 5V tol, CMOS, Input, 50K Pull Down HCE1 tol, CMOS, Input, 50K Pull Up HCE2- 122 5V tol, CMOS, Input, 50K Pull Up HD0-15 ...
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Radio Interface and General Purpose Port Pins PIN NAME PIN NUMBER TXD 17 CMOS Output, 2mA, 50K Pull Down TXC 18 5V tol, CMOS, BiDir 2mA, ST RXD 19 CMOS Input RXC 20 CMOS Input, ST PJ0 31 CMOS BiDir, ...
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Power PIN NAME PIN NUMBER VCC_CORE3 14, 25, 39, 53 VCC_IO3 66, 83, 98. 124 VCC_IO5 105 VSS_CORE3 13, 24, 37 VSS_IO3 42, 52, 67, 82, 97, 115 TRST Schmitt Trigger (Hysteresis Three-State. Signals ending ...
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Special Hardware Functions for Port Pins PJ0 SCK MMI serial clock in or out PJ1 SDO/SDIO MMI serial data out or I/O MOSI SPI Master Out/Slave In PJ2 SDI/MISO MMI serial data in SDDIR MMI (SDIO) data direction PJ3 SDE0 ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications (Continued) PARAMETER SYNTHESIZER SPCLK Period SPCLK Width Hi SPCLK Width Lo SYNCLE to Rising Edge SPCLK SPDATA Hold Time from Falling Edge of SPCLK SPCLK Falling Edge to SYNLE Inactive SERIAL PORT - HFA3824A/HFA3860B SPCLK Clock Period ...
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AC Electrical Specifications (Continued) PARAMETER SIOIS16N Delay Falling from Address SIOIS16N Delay Rising from Address SWAITN Delay Falling from IOWRN SWAITN Width Time SIOWRN High from SWAITN High RADIO TX DATA - TX PATH TXC Rising to TXD TXC Period ...
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Waveforms OSC MCLK (INTERNAL) 44MHz 23ns OSC 10ns (NOTE 10) MCLK (INTERNAL) QCLK (INTERNAL) MCLKOUT 11.5ns ADDRESS, RAMCS_ 17ns MOE_ MD0-15 READ DATA MWEH/L_ MD0-15, WRITE DATA NOTE: 10. Timing delays between OSC and internal clocks are shown for information ...
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Waveforms (Continued) 44MHz 23ns OSC 10ns (NOTE 12) 14.67MHz MCLK (INTERNAL) QCLK (INTERNAL) MCLK OUT 11.5ns ADDRESS, RAMCS_ 17ns MOE_ MD0-15 READ DATA MWEH/L_ MD0-15 WRITE DATA MBUS READ CYCLE NOTES: 11. 14.67MHz requires an odd divisor in the prescaler. ...
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Waveforms (Continued) SPCLK SYNLE SPCSPWR t D1 SPDATA SPCLK SPCSX SPAS SPREAD (READ) SPDATA (READ) SPREAD (WRITE) SPDATA (WRITE) 12 Preliminary - HFA3841 CYC t D2 D[n] D[n -1] D[n -2] D[2] FIGURE 5. SYNTHESIZER ...
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Waveforms (Continued) SA[15:0] SREGN SCE( SIORDN t SUA SINPACKN SIOIS16N SWAITN D[15:0] SA[15:0] SREGN SCE ( SIOWRN SIOIS16N SWAITN t SUIOWR D[15:0] 13 Preliminary - HFA3841 t SUREG t HREG I t SUCE HCE t WIORD ...
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Waveforms (Continued) TXDATA TXCLK t TX_RDY TX_PE2 TXD TXCLK MCLK TXCLK_INT TXCLK_INT2 TXCLK_ONE _SHOT TXD_INT 14 Preliminary - HFA3841 TX_RDY FIGURE 9. TX PATH A t DTXD t CHM t CLM A B FIGURE 10 TXCLK t ...
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Waveforms (Continued) RXDATA RXCLK t SURX_RDY RX_RDY RX_PE2 CCA RXDATA RXCLK RXD_INT MCLK RXCLK_INT RXCLK_INT2 RXCLK_ONE _SHOT 15 Preliminary - HFA3841 FIGURE 11. RX PATH A t RCHM t SURXD t RCLM A FIGURE 12. t HRX_RDY t DRX_PE2 t ...
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HFA3841 System Overview I/O BUS HOST SYSTEM (I/O DRIVER) LAN DISTRIBUTION SYSTEM HFA3841 MD0..15 MA1..17 NVCS_ MOE_ MWEL_ MA0/MWEH_ RAMCS_ External Memory Interface An external memory space is provided for firmware and for buffers that are used for temporary storage ...
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The HFA3841 was designed to implement 16-bit wide memory by using two 8-bit RAM chips. The HFA3841 provides high and low write enable signals (MWEH_ and MWEL_), and a single output enable (MOE_). This allows a direct connection, enabling a ...
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If another read cycle has invalidated the pre-read, then a memory arbitration delay will occur on the next buffer access path read cycle. HIREQ- Immediately after reset, the ...
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Buffer Access Paths The HFA3841 has two independent buffer access paths, which permits concurrent read and write transfers. The firmware provides dynamic memory allocation between Transmit and Receive, allowing efficient memory utilization. On-the-fly allocation of (128-byte) memory blocks as needed ...
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PHY Interface The HFA3841 is intended to support the PRISM family of Baseband processors with no additional components. This family currently includes the HFA3860B and HFA3861 DSSS baseband processors and the other ICs in the PRISM WLAN chip set. (Other ...
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SCLK SDI, R/W, SD (AS OUTPUT) R/W SD TABLE 1. BBP CONTROL PORT AC ELECTRICAL SPECIFICATIONS PARAMETER SYMBOL SCLK Clock Period t SCP SCLK Width Hi or Low t SCW Setup to SCLK + Edge t SCS (SD, ...
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In transmit mode, the HFA386X is used in the mode where it generates the PLCP header internally and only the MPDU is passed from HFA3841. In receive, the HFA386X is used in the mode where it passes the PLCP header ...
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TABLE 2. BBP RECEIVE PORT AC ELECTRICAL SPECIFICATIONS PARAMETER SYMBOL MIN RX_PE Inactive Width t 70 RLP RXC Period (11MBps t 77 RCP Mode) RXC Width Hi or Low t 31 RCD (11MBps Mode) RXC to RXD t 20 RDD ...
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TXC TX_PE TXD TXRDY NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXC. TX_PE OUT, OUT TXRDY TXC TXD Power Sequencing The HFA3841 provides a number of firmware controlled ...
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PE1 PE2 TR_SW TR_SW_BAR TX_PE TX_RDY PA_PE FIGURE 24. TRANSMIT CONTROL SIGNAL SEQUENCING TABLE 4. TRANSMIT CONTROL TIMING SPECIFICATIONS PARAMETER SYMBOL DELAY PE2 to TR Switch PE2 to BBP TX_PE t TBD D2 PE2 to PA_PE t ...
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... HFA3683 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4634. [6] PC Card Standard 1996, PCMCIA/JEIDA. [7] AN9874 Application Note, Intersil Corporation, “ISA Plug and Play with the HFA3841”. [8] AN9844 Application Note, Intersil Corporation, “HFA3841 to PRISMII Connections”, AnswerFAX Doc. ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...