PCK2509SL NXP Semiconductors, PCK2509SL Datasheet

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PCK2509SL

Manufacturer Part Number
PCK2509SL
Description
Manufacturer
NXP Semiconductors
Datasheet
Product specification
ICL03 — PC Motherboard ICs; Logic Products Group
PCK2509SL
50–150 MHz 1:9 SDRAM clock driver
INTEGRATED CIRCUITS
2000 Dec 01

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PCK2509SL Summary of contents

Page 1

... PCK2509SL 50–150 MHz 1:9 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group INTEGRATED CIRCUITS 2000 Dec 01 ...

Page 2

... This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV The PCK2509SL is characterized for operation from +70 C. PIN CONFIGURATION 1 AGND ...

Page 3

... AV PWR CC bypassed and CLK is buffered directly to the device outputs. Clock input. CLK provides the clock signal to be distributed by the PCK2509SL clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output 24 CLK IN signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal ...

Page 4

... FRONT SIDE 2000 Dec 01 PLL A[L]VC A[L]VC A[L]VC PCK2509SL The PLL clock distribution device and A[L]VC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation 4 Product specification PCK2509SL 3 1Y0 4 1Y1 5 1Y2 8 1Y3 9 1Y4 21 2Y0 ...

Page 5

... GND 3 outputs: LOW or HIGH O One input at V – 0.6V; CC 3.3 to 3.6 other inputs GND CC 3 GND GND Product specification PCK2509SL LIMITS UNIT UNIT MIN MAX < 0 –0.5 +4.6 V –50 mA –0.5 6 –0 0 –65 +150 ...

Page 6

... FBIN FBIN Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT 60 MHz) Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT = static t jitter ). phase error – (cycle-cycle) 6 Product specification PCK2509SL MAX UNIT 150 MHz 3 UNIT UNIT MIN ...

Page 7

... SW00435 Figure 2. Supply current vs. clock frequency C (LF) 200 150 100 50 0 150 SW00433 Figure 4. Cycle-to-cycle jitter vs. clock frequency 8 10 SW00439 7 Product specification PCK2509SL 3 amb CLOCK FREQUENCY (MHz) SW00434 3 pF amb 80 90 ...

Page 8

... ANY Y ANY Y 2000 Dec 01 INPUT OUTPUT 500 VOLTAGE WAVEFORMS & PHASE ERROR TIMES Figure 6. Load Circuit and Voltage Waveforms t phase error t SK(0) t SK(0) Figure 7. Phase Error and Skew Calculations 8 Product specification PCK2509SL 0 ...

Page 9

... Philips Semiconductors 50–150 MHz 1:9 SDRAM clock driver TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 2000 Dec 01 9 Product specification PCK2509SL SOT355-1 ...

Page 10

... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 2000 Dec 01 [1] Copyright Philips Electronics North America Corporation 2000 Document order number: 10 Product specification PCK2509SL All rights reserved. Printed in U.S.A. Date of release: 12-00 9397 750 07846 ...

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