M38049FFFP Mitsumi Electronics, Corp., M38049FFFP Datasheet
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M38049FFFP
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M38049FFFP Summary of contents
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DESCRIPTION The 3803/3804 group is the 8-bit microcomputer based on the 740 family core technology. The 3803/3804 group is designed for household products, office automation equipment, and controlling systems that require ana- log signal processing, including the A-D converter and ...
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PIN CONFIGURATION (TOP VIEW ...
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... Fig. 4 3804 group pin configuration SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M38049FFFP/ M38047M8-XXXFP/ Package type : 64P6N-A/64P6Q ...
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FUNCTIONAL BLOCK Fig. 5 3803 group functional block diagram 4 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ...
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Fig. 6 3804 group functional block diagram MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 5 ...
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PIN DESCRIPTION Table 1 Pin description (3803 group) Pin Name •Apply voltage of 2.7 V – 5 Vcc, and Vss. Power source •In the flash memory version, apply voltage of ...
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Table 2 Pin description (3804 group) Pin Name •Apply voltage of 2.7 V – 5 Vcc, and Vss. Power source •In the flash memory version, apply voltage of 4.0 V ...
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PART NUMBERING – Fig. 7 Part numbering 8 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ...
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GROUP EXPANSION GROUP EXPANSION Mitsubishi plans to expand the 3803/3804 group as follows. Memory Type Support for mask ROM and flash memory versions. Memory Size Flash memory size ......................................................... 60 K bytes Mask ROM size ................................................. ...
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... M38049MC-XXXSP (49022) M38049MC-XXXFP M38049MC-XXXHP M38039MF-XXXSP M38039MF-XXXFP M38039MF-XXXHP 61440 M38049MF-XXXSP (61310) M38049MF-XXXFP M38049MF-XXXHP M38039FFSP M38039FFFP M38039FFHP 61440 M38049FFSP M38049FFFP M38049FFHP 10 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RAM size (bytes) Package 64P4B 64P6N-A 64P6Q-A Mask ROM version 640 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A ...
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FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3803/3804 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and ma- chine instructions or the 740 Family Software Manual for details on the instruction ...
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Interrupt request – ...
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The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed ...
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Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B Fig.11 Structure of CPU mode register 14 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS ...
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MISRG (1) Bit 0 of address 0010 Oscillation stabilizing time set af- 16: ter STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt ...
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MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and ...
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I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or ...
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Table 7 I/O port function of 3804 group Name Pin P0 /AN –P0 /AN CMOS compatible input level Port Port P1 P1 /INT CMOS 3-state output /INT –P1 2 ...
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Pull-up control bit ...
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Pull-up control bit ...
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Pull-up control bit Serial I/O2 synchronous clock selection bit ...
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Ports P0 Direction register ...
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Pull-up control bit Serial I/O2 synchronous clock selection bit ...
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Fig. 22 Structure of port pull-up control register (1) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P0 pull-up control register ( ...
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Fig. 23 Structure of port pull-up control register (2) 28 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P2 pull-up control register ( ...
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Fig. 24 Structure of port pull-up control register (3) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P4 pull-up control register ( ...
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Fig. 25 Structure of port pull-up control register (4) 30 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P6 pull-up control register (PULL6: address 0FF6 ) 16 P6 pull-up control bit pull-up 1: Pull-up ...
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INTERRUPTS The 3803 group’s interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software. The 3804 group’s interrupts occur by 16 sources among 23 sources: nine external, thirteen internal, ...
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Table 8 Interrupt vector addresses and priority of 3803 group Vector Addresses (Note 1) Interrupt Source Priority High 1 FFFD Reset (Note FFFB INT 0 16 Timer Z FFF9 INT Serial I/O1 4 FFF7 ...
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Table 9 Interrupt vector addresses and priority of 3804 group Vector Addresses (Note 1) Interrupt Source Priority High 1 FFFD Reset (Note FFFB INT 0 16 Timer Z FFF9 INT Serial I/O1 4 FFF7 ...
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Interrupt edge selection register ( ...
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Interrupt edge selection register ( ...
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TIMERS 8-bit Timers The 3803/3804 group has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. ...
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Event counter mode Mode selection This mode can be selected by setting “10” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY ...
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X “ ” ...
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Fig. 30 Structure of timer XY mode register 40 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b 0 Timer XY mode register (TM : address 0023 ) 16 Timer X operating mode bits Timer ...
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Fig. 31 Structure of timer 12, X and timer Y, Z count source selection registers SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b 0 Timer 12, X count source selection register (T12XCSS : address 000E ) 16 Timer 12 ...
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Timers The timer 16-bit timer. When the timer reaches “0000 underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, ...
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Pulse period measurement mode Mode selection This mode can be selected by setting “010” to the timer Z operat- ing mode bits (bits and setting “0” to the timer/event counter mode switch bit (b7) of the ...
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Programmable waveform generating mode Mode selection This mode can be selected by setting “100” to the timer Z operat- ing mode bits (bits and setting “0” to the timer/event counter mode switch bit (b7) of the ...
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Note: When selecting the modes except the timer/event Fig. 33 Structure of timer Z mode register 46 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Z mode register (TZM : address 002A ) ...
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SERIAL I/O Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation ...
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Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and ...
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I/O1 Control Register (SIO1CON)] 001A 16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B 16 The UART control register consists of four control bits (bits 0 to ...
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Notes concerning serial I/O1 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation Note Clear the serial I/O enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). Reason Since transmission is ...
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S output of reception side RDY Note When signals are output from the S pin on the reception side RDY by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, ...
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Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by ...
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Serial I/O3 Serial I/O3 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation ...
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Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit of the serial I/O3 control register to “0”. Eight serial data transfer formats can be selected, and ...
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I/O3 Control Register (SIO3CON)] 0032 16 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 0033 16 The UART control register consists of four control bits (bits 0 to ...
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Notes concerning serial I/O3 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation Note Clear the serial I/O enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). Reason Since transmission is ...
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S output of reception side RDY Note When signals are output from the S pin on the reception side RDY by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, ...
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PULSE WIDTH MODULATION (PWM) The 3803/3804 group has PWM functions with an 8-bit resolution, based on a signal that is the clock input X or that clock input di- IN vided the clock input X or that ...
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PWM control register (PWMCON : address 002B ...
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A-D CONVERTER [A-D Conversion Register 1, 2 (AD1, AD2)] 0035 , 0038 16 16 The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous ...
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D-A CONVERTER The 3803/3804 group has two internal D-A converters (DA1 and DA2) with 8-bit resolution. The D-A conversion is performed by setting the value in each D-A conversion register. The result of D-A conversion is output from the DA ...
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WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer ...
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MULTI-MASTER I C-BUS INTERFACE 2 The 3804 group has the multi-master I C-BUS interface. 2 The multi-master I C-BUS interface is a serial communications cir- 2 cuit, conforming to the Philips I C-BUS data transfer format. This interface, offering ...
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C Data Shift Register (S0)] 0011 2 The I C data shift register (S0: address 0011 register to store receive data and write transmit data. When transmit data is written into this register transferred to the ...
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C Clock Control Register (S2)] 0015 2 The I C clock control register (S2: address 0015 ACK control, SCL mode and SCL frequency. •Bits SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. ...
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C Control Register (S1D)] 0014 2 The I C control register (S1D: address 0014 ) controls data com- 16 munication format. •Bits Bit counter (BC0–BC2) These bits decide the number of bits for the next ...
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C Status Register (S1)] 0013 16 2 The I C status register (S1: address 0013 ) controls the I 16 interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out ...
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Communication mode specification bit (transfer direc- tion specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is ...
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START Condition Generating Method When writing “1” to the MST, TRX, and BB bits of the I register (S1: address 0013 ) at the same time after writing the 16 2 slave address to the I C data shift register ...
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START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 72, 73, and Table 14. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal ...
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C START/STOP Condition Control Register (S2D)] 0016 16 2 The I C START/STOP condition control register (S2D: address 0016 ) controls START/STOP condition detection. 16 •Bits START/STOP condition set bit (SSC4–SSC0) SCL release time, setup ...
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C Special Mode Status Register (S3)] 0012 16 2 The I C special mode status register (S3: address 0012 2 sists of the flags indicating I C operating state in the I 2 mode, which is set by ...
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C Special Mode Control Register (S3D)] 0017 16 2 The I C special mode control register (S3D: address 0017 trols special functions such as occurrence timing of reception interrupt request and extending slave address comparison to 3 bytes. ...
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Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. 7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit ...
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Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of ...
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Precautions when using multi-master I BUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master 2 I C-BUS interface are described below. 2 • ...
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RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an "L" level for 16 cycles or more Then the RESET pin is returned "H" level (the power source voltage should be ...
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Address 0000 ( ...
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CLOCK GENERATING CIRCUIT The M38039FFSP/FP has two built-in oscillation circuits. An oscil- lation circuit can be formed by connecting a resonator between X and X (X and X ). Use the circuit constants in ac- IN OUT CIN COUT cordance ...
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CIN COUT IN OUT CIN COUT IN OUT Fig. 82 Ceramic resonator circuit CIN COUT IN OUT Open Open External oscillation External oscillation circuit circuit V ...
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“1” “ 0 ” Main clock division ratio selection ...
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(φ “ 1 ”← →“ 0 ” C ...
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FLASH MEMORY MODE The 3803/3804 group has the flash memory mode in addition to the normal operation mode (microcomputer mode). The user can use this mode to perform read, program, and erase operations for the internal flash memory. The 3803/3804 ...
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Table 18 Pin description (flash memory parallel I/O mode) Input Pin Name /Output Power supply — CNV V input Input SS PP _____ RESET Reset input Input X Clock input Input IN X Clock output ...
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Read-only Mode The microcomputer enters the read-only mode by applying V to the V pin. In this mode, the user can input the address memory location to be read and the control signals at the timing V ...
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Read command The microcomputer enters the read mode by inputting command code “00 ” in the first cycle. The command code is latched into 16 the internal command latch at the rising edge of the WE input. When the address ...
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Program command The microcomputer enters the program mode by inputting com- mand code “40 ” in the first cycle. The command code is latched 16 into the internal command latch at the rising edge of the WE input. When the ...
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Erase command The erase command is executed by inputting command code 20 in the first cycle and command code 20 again in the second 16 cycle. The command code is latched into the internal command ___ latch at the rising ...
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Reset command The reset command provides a means of stopping execution of the erase or program command safely. If the user inputs command code FF in the second cycle after inputting the erase or program 16 command in the first ...
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Program START ADRS = first location WRITE PROGRAM COMMAND WRITE PROGRAM DATA DURATION = WRITE PROGRAM-VERIFY COMMAND DURATION = 6 ...
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Table 20 DC ELECTRICAL CHARACTERISTICS (T Symbol Parameter I SB1 V supply current (at standby SB2 I V supply current (at read) CC1 supply current (at program) CC2 supply current (at erase) ...
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Flash memory mode 2 (serial I/O mode) The flash memory version of the 3803/3804 group has a function to serially input/output the software commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, ...
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Table 23 Pin description (flash memory serial I/O mode) Input Pin Name /Output Power supply — CNV V input Input SS PP _____ RESET Reset input Input X Clock input Input IN X Clock output ...
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Functional Outline (serial I/O mode) In the serial I/O mode, data is transferred synchronously with the clock using serial input/output. The input data is read from the SDA pin into the internal circuit synchronously with the rising edge of the ...
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Program command Input command code 40 in the first transfer. Proceed and input 16 the low-order 8 bits and the high-order 8 bits of the address and then program data. Programming is initiated at the last rising edge of the ...
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Erase command Input command code 20 in the first transfer and command code 16 20 again in the second transfer. When this is done, the 3803/ 16 3804 group executes an erase command. Erase is initiated at the last rising ...
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Error check command Input command code 80 in the first transfer, and the 3803/3804 16 group outputs error information from the SDA pin, beginning at the next falling edge of the serial clock. If the LSB bit of the 8-bit ...
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DC ELECTRICAL CHARACTERISTICS -relevant standards during read, program, and erase are the same as in the parallel input/output mode for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes. IL ...
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Flash memory mode 3 (CPU reprogramming mode) The 3803/3804 group has the CPU reprogramming mode where a built-in flash memory is handled by the central processing unit (CPU). In CPU reprogramming mode, the flash memory is handled by writing ...
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CPU reprogramming mode operation procedure The operation procedure in CPU reprogramming mode is de- scribed below. < Beginning procedure > Apply the CNVss/V pin for reset release. PP Set the CPU mode register (see Figure 103). After ...
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Program command When “40 ” is written to the flash command register, the 3803/ 16 3804 group enters the program mode. Subsequently to this, if the instruction (for instance, STA or LDM instruction) for writing byte data in the address ...
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Program START ADRS = first location WRITE PROGRAM COMMAND WRITE PROGRAM DATA WAIT ERASE PROGRAM BUSY FLAG = 0 YES WRITE PROGRAM-VERIFY COMMAND DURATION = ...
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NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” Af- ter a reset, initialize flags which affect program execution. In ...
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NOTES ON USAGE Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (V pin) and GND pin (V pin), and between power ...
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ELECTRICAL CHARACTERISTICS Table 26 Absolute maximum ratings Symbol Parameter V Power source voltage CC S Input voltage P0 – – – – ...
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Table 27 Recommended operating conditions (V = 2 – °C, unless otherwise noted Symbol Power source voltage (f(X ) 8.4 MHz Power source voltage (f(X ) 12.5 MHz) CC ...
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Table 28 Recommended operating conditions (V = 2 – °C, unless otherwise noted Symbol I “H” total peak output current OH(peak) I “H” total peak output current OH(peak) I “L” total ...
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Table 29 Electrical characteristics (V = 2 – °C, unless otherwise noted Symbol Parameter “H” output voltage P0 – – ...
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Table 30 Electrical characteristics (flash memory version 4 – °C, unless otherwise noted Symbol Parameter I Power source current CC 120 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP ...
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Table 31 Electrical characteristics (mask ROM version 2 – °C, unless otherwise noted Symbol Parameter I Power source current CC MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT ...
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Table 32 A-D converter characteristics ( 2 REF CC SS 10-bit A-D mode (when conversion mode selection bit (bit 7 of address 0038 Symbol Parameter – ...
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TIMING REQUIREMENTS Table 35 Timing requirements ( 4 – °C, unless otherwise noted Symbol t (RESET) Reset input “L” pulse width W Main clock ...
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Table 36 Timing requirements ( 2 – °C, unless otherwise noted Symbol t (RESET) Reset input “L” pulse width Main ...
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Table 37 Switching characteristics 4 – °C, unless otherwise noted Symbol Parameter CLK1 Serial I/O1, serial I/O3 clock output ...
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Measurement output pin Fig. 105 Circuit for measuring output switching characteristics (1) 126 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ...
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Table 39 Multi-master I C-BUS bus line characteristics Symbol Parameter t Bus free time BUF t Hold time for START condition HD;STA t Hold time for S clock = “0” LOW CL t Rising time of both S and ...
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PACKAGE OUTLINE 64P6N-A EIAJ Package Code JEDEC Code QFP64-P-1414-0.80 – 64P4B MMP EIAJ Package Code JEDEC Code SDIP64-P-750-1.78 – SEATING PLANE MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS ...
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MMP 64P6Q-A EIAJ Package Code JEDEC Code LQFP64-P-1010-0.50 – HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit ...
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REVISION DESCRIPTION LIST Rev. No. 0.1 First Edition; Only including overview. The issue including all information will be released in April. 1.0 Functional descriptions are added. 2.0 All pages; “PRELIMINARY Notice: This is...” eliminated. Page 9; Product names are added ...
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REVISION DESCRIPTION LIST Rev. No. 2.0 Page 117; Table 28 is revised for only flash memory version. Table 29 is added. 3.0 Page 1; “ Minimum instruction execution time” of “FEATURES” is revised. Page 1; “ Memory size” of “FEATURES” ...
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REVISION DESCRIPTION LIST Rev. No. 3.0 Page 38; Explanations of “ Mode selection” and “ Explanation of operation” of “(3) Event counter mode” of “Timer X and Timer Y” are revised. Page 38; “ Interrupt” of “(3) Event counter mode” ...
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REVISION DESCRIPTION LIST Rev. No. 3.0 Page 63; Explanations of “7. Transmit interrupt request when transmit enable bit is set” are revised. Page 68; Explanations of “D-A CONVERTER” are partly eliminated. Page 70; Figure 64 is partly revised. 2 Page ...
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REVISION DESCRIPTION LIST Rev. No. 3.0 Page 124; Limits and unit of tw(RESET) into Table 36 are revised. Page 125; Limits CLK1 3803/3804 GROUP DATA SHEET Revision Description ), into Tables 37 and ...