BR24C04 Rohm, BR24C04 Datasheet
BR24C04
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BR24C04 Summary of contents
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... Automatic Word Address Incrementing – Sequential register read • Automatic erase-before-write. • Page write buffer for bytes: BR24C01A / bytes: BR24C02 / bytes: BR24C04 / F • DATA security –Inhibit to write at low • Noise filters at SCL and SDA pins. ...
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... Memory ICs • Over view The BR24C01A / AF, BR24C02 / F, and BR24C04 / F are 2-wire serial EEPROMs which are electrically programmable. The configurations are as follows: BR24C01A / AF: 128 8 bit 1K serial EEPROM BR24C02 / F: 256 8 bit 2K serial EEPROM BR24C04 / F: 512 8 bit 4K serial EEPROM • Block diagram BR24C01A / AF ...
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... Min. Typ. Max. 0.7V — — CC — — 0. — — 0.4 – 10 — 10 – 10 — 10 — — 1.0 — — 2.0 — — 100 BR24C04 / BR24C04F Unit Unit 2.7 to 5.5V) Unit Conditions V — V — 3.0mA (SDA ...
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... DAT 0 — DAT 250 — 0.3 — 0.3 — STO 4.7 — 4.7 — BUF t — — WR1 t — — WR2 tI — — BR24C04 / BR24C04F Max. Unit — s — s 1.0 s 0.3 s — s — s — ns — ns 3.5 s — s — s — 0.1 s ...
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... STA HD START BIT • Data is read on the rising edge of SCL. • Data is output in synchronization with the falling edge of SCL. Fig.1 Synchronized data input / output timing ACK D0 Stop condition Fig.2 Write cycle timing BR24C04 / BR24C04F HIGH t LOW t : DAT ...
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... BR24C01A / BR24C01AF / BR24C02 / BR24C02F / With the BR24C04 / F Make sure the slave address is output from the master in continuation with the start condition. The upper four bits of the slave address are used to determine the device type. The device code for this IC is fixed at “ ...
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... SDA ( -COM output data) SDA (BR24C01A / AF, BR24C02 / F, BR24C04 / F output data) BR24C01A / BR24C01AF / BR24C02 / BR24C02F / When data is being written to this IC, a LOW acknowl- edge signal (ACK signal) is output after the receipt of each eight bits of data (word address and write data). ...
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... Word Slave address address Fig.5 Byte write cycle (BR24C02 / WA7 WA6 Slave address Word address Fig.6 Byte write cycle (BR24C04 / F) BR24C04 / BR24C04F Stop condition WA0 D7 D0 Write data ACK signal (output) Stop condition ...
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... WA0 D7 D0 Word Write address data n ACK signal (output) Fig.8 WA7 WA0 D7 D0 Word Write address data n ACK signal (output) Fig.9 BR24C04 / BR24C04F Stop condition D7 D0 Write data ( Stop condition Write data Stop condition D7 D0 Write data ...
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... Slave address ACK signal (output) Fig.11 Current read cycle (BR24C02 / Slave address ACK signal (output) Fig.12 Current read cycle (BR24C04 / F) BR24C04 / BR24C04F Stop condition Read data ACK signal (input) Stop condition ...
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... ACK signal (output) Fig.14 Random read cycle (BR24C02 / F) Start condition WA7 WA0 Word Slave address address ACK signal (output) Fig.15 Random read cycle (BR24C04 / F) BR24C04 / BR24C04F Stop condition Read data (add. h) Stop condition Read ...
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... SDA Slave address Fig.18 Sequential read cycle (BR24C04 / F) • When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master ( -COM), the next word address data can be read. [All words can be read] • This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) using the SCL signal HIGH. • ...
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... BR24C01A / BR24C01AF / BR24C02 / BR24C02F / OFF -I features, which have been appended as measuring data 0 – 40 Note: All memory array data are set to “FF” status at time of shipping. BR24C04 / BR24C04F —I features (Note: Typ 0.1 0.2 ...