XPC850DECZT50B Freescale Semiconductor, Inc, XPC850DECZT50B Datasheet
XPC850DECZT50B
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XPC850DECZT50B Summary of contents
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Advance Information MPC850EC/D Rev. 0.2, 04/2002 MPC850 (Rev. A/B/C) Communications Controller Hardware Specifications This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC timing specifications for revision A,B, and C of the MPC850. This document contains the ...
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One USB channel • Two serial management controllers (SMCs) 2 • One I C port • One serial peripheral interface (SPI). Table 1 shows the functionality supported by the members of the MPC850 family. Number of Part SCCs Supported ...
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Part II Features Figure block diagram of the MPC850, showing its major components and the relationships among those components: Figure 1. MPC850 Microprocessor Block Diagram The following list summarizes the main features of the MPC850: • Embedded ...
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Caches are two-way, set-associative – Physically addressed – Cache blocks can be updated with a 4-word line burst – Least-recently used (LRU) replacement algorithm – Lockable one-line granularity — ...
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Interrupt can be masked on reference match and event capture • Interrupts — Eight external interrupt request (IRQ) lines — Twelve port pins with interrupt capability — Fifteen internal interrupt sources — Programmable priority among SCCs and USB — ...
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Supports either transparent or HDLC protocols for each channel — Independent TxBDs/Rx and event/interrupt reporting for each channel • One universal serial bus controller (USB) — Supports host controller and slave modes at 1.5 Mbps and 12 Mbps • ...
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The MPC850 can compare using the =, , <, and > conditions to generate watchpoints — Each watchpoint can generate a breakpoint internally • 3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins. Part III Electrical ...
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Part IV Thermal Characteristics Table 3 shows the thermal characteristics for the MPC850. Characteristic 1 Thermal resistance for BGA Thermal Resistance for BGA (junction-to-case) 1 For more information on the design of thermal vias on multilayer boards and BGA layout ...
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Table 5. DC Electrical Specifications (continued) Characteristic Input low voltage EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins) Input leakage current, Vin = 3.6V (Except TMS, TRST, DSCK and ...
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Layout Practices For most applications P < 0.3 • I/O between P and T is 273 Solving equations (1) and (2) for K gives: • ...
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Num Characteristic B1 CLKOUT period B1a EXTCLK to CLKOUT phase skew (EXTCLK > 15 MHz and MF <= 2) B1b EXTCLK to CLKOUT phase skew (EXTCLK > 10 MHz and MF < 10) B1c CLKOUT phase jitter (EXTCLK > 2 ...
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Layout Practices Table 6. Bus Operation Timing Num Characteristic B11 CLKOUT to TS, BB assertion B11a CLKOUT to TA, BI assertion, (When driven by the memory controller or PCMCIA interface) B12 CLKOUT to TS, BB negation B12a CLKOUT to TA, ...
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Table 6. Bus Operation Timing Num Characteristic B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, ...
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Layout Practices Table 6. Bus Operation Timing Num Characteristic B29b CS negated to D[0–31], DP[0–3], high-Z GPCM write access, ACS = 00, TRLX = 0 & CSNT = 0 B29c CS negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX ...
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Table 6. Bus Operation Timing Num Characteristic B30b WE[0–3] negated to A[6–31] invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A[6–31] Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or ...
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Layout Practices Table 6. Bus Operation Timing Num Characteristic B32b CLKOUT rising edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM B32c CLKOUT rising edge to BS valid - as requested ...
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Table 6. Bus Operation Timing Num Characteristic B37 UPWAIT valid to CLKOUT falling 10 edge B38 CLKOUT falling edge to UPWAIT 10 valid B39 AS valid to CLKOUT rising edge 11 B40 A[6–31], TSIZ[0–1], RD/WR, BURST, valid to CLKOUT rising ...
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Layout Practices 8 The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data ...
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Figure 3 provides the timing for the external clock. Figure 4 provides the timing for the synchronous output signals. CLKOUT Output Signals Output Signals Output Signals Figure 4. Synchronous Output Signals Timing MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Figure 3. ...
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Layout Practices Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals. Figure 5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing Figure 6 provides the timing for the synchronous input signals. CLKOUT , , , ...
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Figure 7 provides normal case timing for input data. Figure 7. Input Data Timing in Normal Case Figure 8 provides the timing for the input data controlled by the UPM in the memory controller. Figure 8. Input Data Timing when ...
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Layout Practices Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT TS A[6:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00) 22 MPC850 ...
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CLKOUT TS A[6:31] CSx OE D[0:31], DP[0:3] Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications B22a ...
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Layout Practices Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) 24 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...
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Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors. Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Layout Practices 25 ...
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Layout Practices Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) 26 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...
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Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) Figure 16 provides the timing for the external bus controlled by the UPM. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Layout Practices 27 ...
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Layout Practices Figure 16. External Bus Timing (UPM Controlled Signals) Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing 28 MPC850 (Rev. A/B/C) ...
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Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the synchronous external master access controlled by the ...
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Layout Practices Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM. Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 21 provides the timing for the asynchronous external master ...
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Figure 22 provides the interrupt detection timing for the external level-sensitive lines. Figure 22. Interrupt Detection Timing for External Level Sensitive Lines Figure 23 provides the interrupt detection timing for the external edge-sensitive lines. Figure 23. Interrupt Detection Timing for ...
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Layout Practices Num Characteristic CLKOUT to ALE negate time PCWE, IOWR negated to D[0–31] 1 invalid. WAIT_B valid to CLKOUT rising edge. CLKOUT rising edge to WAIT_B invalid. 1 PSST = 1. Otherwise add PSST times cycle time. PSHT = ...
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Figure 25 provides the PCMCIA access cycle timing for the external bus write. Figure 25. PCMCIA Access Cycles Timing External Bus Write Figure 26 provides the PCMCIA WAIT signals detection timing. WAIT_B Figure 26. PCMCIA WAIT Signal Detection Timing MOTOROLA ...
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Layout Practices Table 9 shows the PCMCIA port timing for the MPC850. Num Characteristic CLKOUT to OPx valid HRESET negated to OPx drive IP_Xx valid to CLKOUT rising edge CLKOUT rising edge to IP_Xx invalid 1 OP2 and OP3 only. ...
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Table 10 shows the debug port timing for the MPC850. Num Characteristic DSCK cycle time DSCK clock pulse width DSCK rise and fall times DSDI input data setup time DSDI data hold time DSCK low to DSDO data valid DSCK ...
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Layout Practices Table 11 shows the reset timing for the MPC850. Num Characteristic CLKOUT to HRESET high impedance CLKOUT to SRESET high impedance RSTCONF pulse width Configuration data to HRESET rising edge set up time Configuration data to RSTCONF rising ...
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Figure 32 provides the reset timing for the data bus weak drive during configuration. Figure 32. Reset Timing—Data Bus Weak Drive during Configuration Figure 33 provides the reset timing for the debug port configuration. Figure 33. Reset Timing—Debug Port Configuration ...
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Layout Practices Num Characteristic TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low TCK falling edge to ...
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Figure 36. JTAG TRST Timing Diagram Figure 37. Boundary Scan (JTAG) Timing Diagram Part VIII CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC850. 8.1 PIO AC Electrical ...
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IDMA Controller AC Electrical Specifications Figure 38. Parallel I/O Data-In/Data-Out Timing Diagram 8.2 IDMA Controller AC Electrical Specifications Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42. Num 40 DREQ setup time to clock ...
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Figure 40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the Falling Edge Figure 41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the Falling Edge MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications IDMA Controller AC Electrical Specifications of the Clock ...
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Baud Rate Generator AC Electrical Specifications Figure 42. SDACK Timing Diagram—Peripheral Read 8.3 Baud Rate Generator AC Electrical Specifications Table 15 provides the baud rate generator timings as shown in Figure 43. Table 15. Baud Rate Generator Timing Num 50 ...
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Timer AC Electrical Specifications Table 16 provides the baud rate generator timings as shown in Figure 44. Num 61 TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO high ...
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Serial Interface AC Electrical Specifications Num Characteristic 74 L1xCLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) 75 L1RSYNC, L1TSYNC rise/fall time 76 L1RXD valid to L1xCLK edge (L1RXD setup time) 77 L1xCLK edge to L1RXD invalid (L1RXD hold time) ...
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L1RCLK (FE=0, CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RxD (Input) 76 L1STn (Output) Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Serial Interface AC Electrical Specifications ...
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Serial Interface AC Electrical Specifications L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 46. SI Receive Timing with Double-Speed Clocking (DSC = 1) 46 MPC850 (Rev. ...
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L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) 80a L1TxD BIT0 (Output L1STn (Output) Figure 47. SI Transmit Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Serial Interface AC Electrical Specifications 70 72 TFSD=0 ...
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Serial Interface AC Electrical Specifications L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) 75 L1RSYNC (Input L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 48. SI Transmit Timing with Double Speed Clocking (DSC = ...
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MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Serial Interface AC Electrical Specifications Figure 49. IDL Timing 49 ...
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SCC in NMSI Mode Electrical Specifications 8.6 SCC in NMSI Mode Electrical Specifications Table 18 provides the NMSI external clock timing. Table 18. NMSI External Clock Timing Num 100 RCLKx and TCLKx frequency table) 101 RCLKx and TCLKx width low ...
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Figure 50 through Figure 52 show the NMSI timings. Figure 50. SCC NMSI Receive Timing Diagram Figure 51. SCC NMSI Transmit Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications SCC in NMSI Mode Electrical Specifications 51 ...
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Ethernet Electrical Specifications 8.7 Ethernet Electrical Specifications Table 20 provides the Ethernet timings as shown in Figure 53 to Figure 55. Num 120 CLSN width high 121 RCLKx rise/fall time ( for all specs in this table) ...
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Table 20. Ethernet Timing (continued) Num 133 TENA active delay (from TCLKx rising edge) 134 TENA inactive delay (from TCLKx rising edge) 138 CLKOUT low to SDACK asserted 139 CLKOUT low to SDACK negated 1 The ratios SyncCLK/RCLKx and SyncCLK/TCLKx ...
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SMC Transparent AC Electrical Specifications Figure 55. Ethernet Transmit Timing Diagram 8.8 SMC Transparent AC Electrical Specifications Figure 21 provides the SMC transparent timings as shown in Figure 56. Table 21. Serial Management Controller Timing Num 150 SMCLKx clock period ...
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Figure 56. SMC Transparent Timing Diagram 8.9 SPI Master AC Electrical Specifications Table 22 provides the SPI master timings as shown in Figure 57 and Figure 58. Num 160 MASTER cycle time 161 MASTER clock (SCK) high or low time ...
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SPI Master AC Electrical Specifications Figure 57. SPI Master ( Timing Diagram Figure 58. SPI Master ( Timing Diagram 56 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...
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SPI Slave AC Electrical Specifications Table 23 provides the SPI slave timings as shown in Figure 59 and Figure 60. Num 170 Slave cycle time 171 Slave enable lead time 172 Slave enable lag time 173 Slave clock (SPICLK) ...
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SPI Slave AC Electrical Specifications Figure 59. SPI Slave ( Timing Diagram 58 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...
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Figure 60. SPI Slave ( Timing Diagram 8. Electrical Specifications 2 2 Table 24 provides the I C (SCL < 100 KHz) timings. Num 200 SCL clock frequency (slave) 200 SCL clock frequency (master) 202 ...
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I2C AC Electrical Specifications Table 24. I Num 208 Data setup time 209 SDL/SCL rise time 210 SDL/SCL fall time 211 Stop condition setup time 1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * ...
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Figure 61 shows the I C bus timing. Part IX Mechanical Data and Ordering Information Table 26 provides information on the MPC850 derivative devices. Device Ethernet Support MPC850 N/A MPC850DE Yes MPC850SAR Yes 1 Serial Communication Controller (SCC) 2 ...
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... Frequency (MHz) Temperature (Tj) 50 0°C to 95°C 66 0°C to 95°C 80 0°C to 95°C 50 -40°C to 95° Order Number XPC850ZT50B XPC850DEZT50B XPC850SRZT50B XPC850ZT66B XPC850DEZT66B XPC850SRZT66B XPC850ZT80B XPC850DEZT80B XPC850SRZT80B XPC850CZT50B XPC850DECZT50B XPC850SRCZT50B XPC850CZT66B XPC850DECZT66B XPC850SRCZT66B XPC850CZT80B XPC850DECZT80B XPC850SRCZT80B MOTOROLA ...
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Figure 62 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. PC12 PC14 PB28 PB27 TCK PC15 PA14 PA13 PA12 TMS PB26 PA15 PB30 PB29 PC13 A8 A7 PB31 N/C TDO A11 A9 A12 A6 ...
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Pin Assignments and Mechanical Dimensions of the PBGA Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface. PC14 PB28 PB27 PC12 TCK PC15 PA14 PA13 PA12 TMS PB26 PA15 PB30 PB29 PC13 A8 ...
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Figure 64 shows the non-JEDEC package dimensions of the PBGA. A 0.20 C 256X 0. 0. SEATING PLANE SIDE VIEW e 15X (E1 Figure 64. Package Dimensions for ...
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Pin Assignments and Mechanical Dimensions of the PBGA Figure 65 shows the JEDEC package dimensions of the PBGA. A 0.20 C 256X 0. 0. SEATING PLANE SIDE VIEW e 15X (E1) ...
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Pin Assignments and Mechanical Dimensions of the PBGA Part X Document Revision History Table 28 lists significant changes between revisions of this document. Revision Date 0.1 11/2001 Removed reference to 5 Volt tolerance capability on peripheral interface pins. Replaced SI ...
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HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon ...