M5M44260CTP-7 Mitsumi Electronics, Corp., M5M44260CTP-7 Datasheet
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M5M44260CTP-7
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M5M44260CTP-7 Summary of contents
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DESCRIPTION This is a family of 262144-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization ...
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FUNCTION In addition to normal read,write and read-modify-write operations the M5M44260CJ, TP provides a number of other functions, e.g., Table 1 Input conditions for each mode Operation Lower byte read Upper byte read Word read Lower byte write Upper byte ...
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ABSOLUTE MAXIMUM RATINGS Symbol Parameter Supply voltage V CC Input voltage Output voltage O I Output current O Power dissipation Operating temperature opr Storage temperature T stg RECOMMENDED OPERATING CONDITIONS Symbol Parameter Supply voltage ...
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V CAPACITANCE CC Parameter Symbol Input capacitance, address inputs C I (A) Input capacitance, clock inputs C I (CLK) C Input/Output capacitance, data ports SWITCHING CHARACTERISTICS Symbol t Access time from CAS CAC t Access ...
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TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles) (Ta=0~70˚C, V =5V±10%, V =0V, unless otherwise noted, see notes 6,13,14 Symbol t Refresh cycle time REF t Refresh cycle time * REF t RAS high pulse ...
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Write Cycle (Early Write and Delayed Write) Symbol Write cycle time t WC RAS low pulse width t RAS t CAS low pulse width CAS t CAS hold time after RAS low CSH RAS hold time after CAS low t ...
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Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) Symbol Fast page mode read/write cycle time t PC Fast page mode read write/read modify write cycle time t PRWC RAS low pulse width for read or write cycle t ...
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Timing Diagrams (Note 29) Read Cycle V IH RAS CRP V IH LCAS/UCAS ASR ~ (INPUTS) ...
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Byte Read Cycle V IH RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS ...
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Write Cycle (Early write RAS CRP V IH LCAS/UCAS ASR t RAH V IH ROW ADDRESS ~ ...
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Byte Write Cycle (Early write RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS ...
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Write Cycle (Delayed write RAS CRP V IH LCAS/UCAS ASR ADDRESS ~ (INPUTS) V ...
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Byte Write Cycle (Delayed write RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS ...
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Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR ~ (INPUTS ...
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Byte Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ...
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RAS-only Refresh Cycle V IH RAS CRP V IH LCAS/UCAS ASR V IH ROW ADDRESS ~ (INPUTS) V ...
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CAS before RAS Refresh Cycle, Extended Refresh Cycle * RAS CSR t RPC V IH LCAS/UCAS CPN RCH ...
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Hidden Refresh Cycle (Read RAS CRP V IH LCAS/UCAS ASR ADDRESS ~ (INPUTS) V ...
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Fast Page Mode Read Cycle V IH RAS CRP V IH LCAS/UCAS ASR t RAH V IH ROW ADDRESS ~DQ ...
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Fast Page Mode Byte Read Cycle V IH RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR t RAH V IH ROW ADDRESS V ...
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Fast Page Mode Write Cycle (Early Write RAS CRP V IH LCAS/UCAS ASR ADDRESS ~DQ 1 ...
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Fast Page Mode Byte Write Cycle (Early Write RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS V IL ...
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Fast-Page Mode Write Cycle (Delayed Write RAS CRP V IH LCAS/UCAS ASR ADDRESS ~ ...
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Fast-Page Mode Byte Write Cycle (Delayed Write RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR RAH V IH ROW ADDRESS ...
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Fast Page Mode Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR ADDRESS ~ ...
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Fast Page Mode Byte Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS ...
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Self Refresh Cycle * (Note28 RAS RPC V IH LCAS/UCAS CPN RCH CDD V IH ...
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Note 28 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width ( RAS signal during self refresh RASS period. 1. Distributed refresh during Read/Write operation (A) Timing Diagram Read / ...
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Burst refresh during Read/Write operation (A) Timing diagram Read / Write RAS first refresh cycles Table 3 Read / Write Read / Write Cycle Self Refresh CBR burst t 8.2ms NSB refresh RAS only burst refresh (B) Definition of ...