SAA7111A NXP Semiconductors, SAA7111A Datasheet
SAA7111A
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SAA7111A Summary of contents
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... DATA SHEET SAA7111A Enhanced Video Input Processor (EVIP) Product specification Supersedes data of 1997 May 26 File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1998 May 15 ...
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... FILTER CURVES 18.1 Anti-alias filter curve 18.2 TUF-block filter curve 18.3 Luminance filter curves 18.4 Chrominance filter curves C-BUS START SET-UP 20 PACKAGE OUTLINES 21 SOLDERING 21.1 Introduction 21.2 Reflow soldering 21.3 Wave soldering 21.4 Repairing soldered joints 22 DEFINITIONS 23 LIFE SUPPORT APPLICATIONS 24 PURCHASE OF PHILIPS I 2 Product specification SAA7111A 2 C COMPONENTS ...
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... Low power ( 0.5 W), low voltage (3.3 V), small package (LQFP64 tolerant digital I/O ports. 2 APPLICATIONS Desktop/Notebook (PCMCIA) video Multimedia Digital television Image processing Video phone Intercast. 3 Product specification SAA7111A 2 C-bus for INTERCAST applications 2 C-bus switchable outputs for the digitized 1990’ (ID-Code = 0 F111 02 B) ...
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... The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7111A accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit C-bus controlled ...
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... LUMINANCE CIRCUIT Y/CVBS Y SAA7111A SYNCHRONIZATION CIRCUIT LFCO VREF RTS0 RTS1 RTCO Fig.1 Block diagram. 5 Product specification SAA7111A VPO YUV-to-RGB (0 : 15) CONVERSION AND OUTPUT FORMATTER 52 FEI 31 HREF 2 I C-BUS CONTROL 53 GPSW 2 I C-BUS ...
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... R Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator; a high state indicates that the internal horizontal PLL has locked. 6 Product specification DESCRIPTION 2 C-bit COMPO = 0) or inverse composite blanking 2 C-bus bit OEHV). 2 C-bus bits HDEL1 and HDEL0. 2 C-bus bit RTSE1. SAA7111A ...
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... PAL sequence. 7 Product specification DESCRIPTION 2 C-bus bit RTSE0. 2 C-bus bit OEHV); this signal indicates the vertical 2 C-bus bit OEHV); this signal is used 2 C-bus bits OFTS0 and OFTS1 VPO7 to VPO0. 2 C-bus bit VIPB = 1 VPO15 to VPO8, 2 C-bus control and SAA7111A 2 C-bus 2 C-bus ...
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... For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin to ground. 1998 May C-bus slave address select 48H for write, 49H for read 1 = 4AH for write, 4BH for read. 2 Serial data input/output (I C-bus). 2 Serial clock input/output (I C-bus). Not connect. 8 Product specification DESCRIPTION SAA7111A ...
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... V DDA2 7 AI21 8 V SSA1 9 10 AI12 V DDA1 11 AI11 12 V SSS 13 AOUT 14 V DDA0 15 V SSA0 16 1998 May 15 SAA7111A Fig.2 Pin configuration (LQFP64/QFP64). 9 Product specification SAA7111A 48 VPO3 47 VPO4 46 VPO5 45 VPO6 44 VPO7 43 VPO8 42 VPO9 V DDD2 41 V SSD2 40 39 VPO10 38 VPO11 37 VPO12 36 ...
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... Philips Semiconductors Enhanced Video Input Processor (EVIP) 8 FUNCTIONAL DESCRIPTION 8.1 Analog input processing The SAA7111A offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video CMOS ADC (see Fig.5). 8.2 Analog control circuits The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit ...
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... The 16-bit VPO-bus transfers digital data from the output interfaces to a feature box or a field memory, a digital colour space converter (SAA7192 DCSC), a video enhancement and digital-to-analog processor (SAA7165 VEDA2 colour graphics board (Targa-format graphical user interface. 11 Product specification SAA7111A ...
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... Internally the LFCO signal is multiplied by a factor the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor (see Fig.26). 12 Product specification SAA7111A 2 C-bus [subaddress 13, clock C-bus ...
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... Field 1 or 2). After valid data has been read the corresponding F*RDY bit is set to LOW until new data has arrived. The polling frequency has to be slightly higher than the frame or field frequency, respectively. 2 C-bus 13 Product specification SAA7111A BUS INTERFACE OF THE -21 DATA 2 ...
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Acrobat reader. white to force landscape pages to be ... 64 n. SSA1 5 V SSA2 6 AI22 SOURCE CLAMP 8 SWITCH ...
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Acrobat reader. white to force landscape pages to be ... LUM CHR 1 n.c. 58 TRST 59 QUADRATURE TCK TEST 3 DEMODULATOR TDI CONTROL ...
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Acrobat reader. white to force landscape pages to be ... LUM LUMINANCE CIRCUIT CHROMINANCE PREFILTER TRAP PREF BYPS VBLB PREFILTER SYNC LINE 21 TEXT ...
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... Fig. 37) 1 SWLO BCLO1 BCLO0 SWLO VBP0 VBP4 1 0 VBP0 1 1 VBP4 REG EN CLOCK 0 17 Product specification SAA7111A 0 MUX BYP REGISTER MUX BYP REGISTER REG VBP4 CLOCK 0 VBP0 MGG064 VPO15 to 8 VIPB 2 I C-bus VPO7 to 0 ...
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... CREFOUT CREFINT VREF VREF = VREF = (always HIGH) Fig.10 CREF output signal generation. 18 Product specification SAA7111A REG HREF CLK0 0 REG MUX VREF 1 CLOCK 0 COMPO MGG065 REG CREF CLOCK 0 MGG066 ...
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... Philips Semiconductors Enhanced Video Input Processor (EVIP) 9 BOUNDARY-SCAN TEST The SAA7111A has built in logic and 5 dedicated pins to support boundary-scan testing which allows board testing without special hardware (nails). The SAA7111A follows the ‘IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture ’ set by the Joint Test Action Group (JTAG) chaired by Philips ...
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... Philips Semiconductors Enhanced Video Input Processor (EVIP) MSB handbook, full pagewidth 31 TDI 0010 4-bit version code 1998 May 1111000100010001 16-bit part number Fig.11 32 bits of identification 20 Product specification LSB 1 0 00000010101 1 TDO 11-bit manufacturer indentification MGL111 code. SAA7111A ...
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... Fig.12 Amplifier curve. ANALOG INPUT ADC 1 0 VBLK <- CLAMP GAIN -> HCL 0 0 SBOT NO CLAMP CLAMP GAIN Fig.13 Clamp and gain flow. 21 Product specification MGC648 ( i i < 256 ( 257 i ( 512 512 1 0 HSY WIPE slow GAIN GAIN fast GAIN MGC647 SAA7111A ...
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... GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV dB AGV Fig.14 Gain flow chart. 22 Product specification 9 DAC LUMA/CHROMA DECODER HSY >254 1/LLC2 0 0 HSY FGV UPDATE GAIN VALUE 9-BIT MGC652 SAA7111A ...
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... CONDITIONS 3.0 3.1 AOSL = [1:0] = 00b; AOUT not connected CE connected to ground (since version 0 for normal video levels 0 (p-p)]; 3 dB termination 27/47 and AC coupling required; coupling capacitor = 22 nF clamping current off 200 23 Product specification SAA7111A MIN. MAX. 0.5 +4.6 0.5 +4.6 0 0.5 DDA (4.6 max.) 0 0.5 DDA 0.5 +5.5 0 0.5 DDD 100 ...
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... CONDITIONS MIN MHz 12.8 0.5 0.7V 0.3 2.0 0.3 2.0 outputs at 3-state SDA/SCL mA) sink current V = max DDD min 2.4 DDD OH 0.5 2.4 at 3-state mode Product specification SAA7111A TYP. MAX 14.3 0.7 1 +0.3V DDD V + 0.5 DDD DDD +0 0.3 DDD +0.8 5 0.4 (0.6) 0 0.5 DDD +0 0.5 DDD 10 ...
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... LLC L at 1.5 V; LLC/LLC2 = nominal frequency XTALI 50 Hz field 60 Hz field PAL BGHI NTSC M; NTSC-Japan PAL M PAL N 3rd harmonic; note 3 25 Product specification SAA7111A MIN. TYP. MAX ...
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... Digital processing delay (LLC CLOCKS) for VBI data is defined in Fig.23 ‘Horizontal timing diagram’. 1998 May 15 CONDITIONS MIN. 3rd harmonic; note OHD;DAT TYPICAL ANALOG DELAY AI22 ADCIN (AOUT) (ns Product specification SAA7111A TYP. MAX. 24.576 1.5 20% 3 and t . Timings and levels refer to ...
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... Fig.16 Clock/data timing (12 and 16-bit CCIR-601 format of the VPO-bus). 1998 May 15 t LLC t LLCL LLCH OHD;DAT t LLC t LLC t LLCL LLCH OHD;CREF t OHD;CREF t dLLC2 OHD;DAT 27 Product specification SAA7111A 2.6 V 1 2.4 V 0.6 V MGC658 2.6 V 1.5 V 0.6 V 2 dLLC2 2.6 V 1.5 V 0.6 V 2.4 V 0.6 V MGC659 ...
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... Fig.18 FEI timing diagram (FEI sampling at CREF = HIGH) for OFTS = 2). 1998 May 15 t LLC t LLCL PD;CREF t OHD;CREF t OHD;CREF t PD;CREF R G OHD;DAT SU;DAT t PDZ t OHD;DAT to 3-state 28 Product specification SAA7111A t LLC t OHD;CREF t OHD;DAT G B HD;DAT t PD MGC656 from 3-state 2.4 V 1.5 V 0.6 V 2.4 V 1.5 V 0.6 V 2.4 V 1.5 V 0.6 V 2.4 V 1.5 V 0.6 V MBH227 ...
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... HD;DAT t PD from 3-state SEQUENCE INCR FSCPLL C-bus bit CDTO. RTCO sequence is generated in LLC/4. Product specification SAA7111A MGC657 (1) DTO RESET RESERVED 50 Hz fields: 235 60 Hz fields: 232 1 68 MGC649 ...
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... VPO Fig.22 FEI timing in CCIR 656 mode [OFTS ( 3]. 1998 May 716 717 718 U716 V716 U718 Fig.21 HREF timing diagram OHD t PDZ Product specification SAA7111A END OF ACTIVE LINE 719 V718 MGC646 MBH766 ...
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... CVBS->VPO 0 720 2/LLC 43 27 2/LLC (1) HS 108 0 23 2/LLC 720 2/LLC 107 0 2 C-bus bit RTSE1 = 0. Fig.23 Horizontal timing diagram. 31 Product specification burst burst (2) sync clipped 12 2/LLC 144 2/LLC 2/LLC 4/LLC 107 16 2/LLC 138 2/LLC 106 MGD701 SAA7111A ...
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... C-bus bit RTSE0 = 0. 2 C-bits VCTR1 and VCTR0 (see Fig.9). 32 Product specification 535 x 2/LLC 318 319 320 335 336 77 x 2/LLC 2 C-bus bit VBLB is set to logic 1. SAA7111A 23 337 MGG069 ...
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... C-bus bits VCTR1 and VCTR0 (see Fig.9). 33 Product specification (10) (11) (8) (9) (20) 520 x 2/LLC 267 268 269 270 271 (270) (271) (272) (273) (274 2/LLC 2 C-bus bit VBLB is set to logic 1. SAA7111A 18 19 (22) (21) (2) 280 281 282 (283) (284) (285) (2) MGG070 ...
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... Z Z Table 4 Clock frequencies active ZERO PHASE CROSS DETECTION DETECTION Fig.26 Block diagram of clock generation circuit. 34 Product specification SAA7111A Clock generation circuit CLOCK FREQUENCY (MHz) XTAL 24.576 LLC LLC2 LLC4 LLC8 LOOP OSCILLATOR FILTER DIVIDER DIVIDER 1/2 1/2 DELAY ...
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... RESINT = internal reset; LLC = line-locked clock output; RES = reset output (active LOW). 1998 May 15 POC V DDA ANALOG CLOCK PLL LLC POC LOGIC 200 s PLL-delay < Fig.27 Power-on control circuit. 35 Product specification SAA7111A POC V DDD DIGITAL POC RES DELAY CLK0 896 LCC 128 LCC digital delay MGC633 ...
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... LLC2 OFTS0 = 0 OFTS1 = 0 RGB888 = 0 SAA7111A (4) RGB (24-BIT note 5 note 6 ...
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... U-COMPONENT yellow 75% 44 yellow 100% black output range (Cb). 2 C-bus bytes BRIG, CONT and SATN. + 128 37 Product specification SAA7111A 2 C-bus bit TCLO = 1. 255 red 100% 240 212 red 75% colourless 128 V-COMPONENT cyan 75% 44 cyan 100 MGC634 c ...
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... Fig.29 VBI data bypass output range. XTAL 54 SAA7111A XTALI 20 Fig.30 Oscillator application. 38 Product specification SAA7111A white black shoulder = black SYNC sync bottom MGD700 For sources not containing black level offset. XTAL 54 SAA7111A XTALI 55 MGG072 b. With external clock. ...
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... MGG071 V n.c. SS Product specification SAA7111A V SS VPO( HREF VREF HS VS RTCO RTS1 RTS0 GPSW AOUT LLC LLC2 CREF RES ...
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... To avoid reflection effects use serial resistors in the clock, sync and data lines. 40 Product specification e.g. 74HCT240 LLC2N MGG073 SAA7111A ...
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... C-bus subaddress 00 has to be initialized with 0 before being read. 1998 May 15 ACK-s SUBADDRESS ACK-s ACK-s DESCRIPTION 41 Product specification SAA7111A ACK-s DATA (N BYTES) SUBADDRESS DATA (N BYTES) read and write; note 3 read and write read and write read and write read only ...
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... VSTA3 VSTA2 VSTO3 VSTO2 (1) (1) (1) (1) (1) (1) (1) F2VAL F2RDY BYTE13 BYTE12 BYTE23 BYTE22 (1) (1) (1) GLIMB WIPA Product specification SAA7111A D1 D0 ID01 ID00 (1) (1) MODE1 MODE0 GAI28 GAI18 GAI11 GAI10 GAI21 GAI20 HSB1 HSB0 HSS1 HSS0 VNOI1 VNOI0 APER1 APER0 BRIG1 ...
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... Product specification ID04 ID03 ID02 CONTROL BITS MODE 2 MODE CONTROL BITS GUDL 2 GUDL SAA7111A ID01 ID00 MODE GUDL ...
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... MGC639 Fig.36 Mode 3; CVBS (automatic gain). AI22 handbook, halfpage CHROMA AI21 LUMA AI12 AI11 MGC641 Fig.38 Mode 5 Y (automatic gain (gain channel 2 fixed to GAI2 level). 44 Product specification SAA7111A CONTROL BITS D7 AND D6 FUSE 1 FUSE AD2 CHROMA LUMA ...
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... Fig.40 Mode 7 Y (automatic gain (gain channel 2 adapted to Y gain). BIT NAME GAI18 GAI28 GAFIX GAFIX HOLDG HOLDG WPOFF WPOFF VBSL VBSL HLNRS HLNRS 45 Product specification SAA7111A AD2 CHROMA LUMA AD1 MGC644 LOGIC LEVEL CONTROL BIT see Table 16 D0 see Table ...
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... CONTROL BITS GAI24 GAI23 GAI22 HSB3 HSB2 SAA7111A GAI11 GAI10 GAI21 GAI20 HSB1 HSB0 ...
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... BIT NAME LOGIC LEVEL VNOI1 0 VNOI0 0 VNOI1 0 VNOI0 1 VNOI1 1 VNOI0 0 VNOI1 1 VNOI0 1 HPLL 0 HPLL 1 VTRC 0 VTRC 1 EXFIL 0 EXFIL 1 FSEL 0 FSEL 1 AUFD 0 AUFD 1 SAA7111A HSS1 HSS0 CONTROL BIT ...
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... APER1 0 APER0 1 APER1 1 APER0 0 APER1 1 APER0 1 UPTCV 0 UPTCV 1 VBLB 0 VBLB 1 BPSS1 0 BPSS0 0 BPSS1 0 BPSS0 1 BPSS1 1 BPSS0 0 BPSS1 1 BPSS0 1 PREF 0 PREF 1 BYPS 0 BYPS 1 48 Product specification SAA7111A CONTROL BIT ...
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... SATN5 SATN4 CONTROL BITS HUEC6 HUEC5 HUEC4 Product specification SAA7111A BRIG3 BRIG2 BRIG1 CONT3 CONT2 CONT1 ...
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... CHBW1 CHBW0 FCTC FCTC DCCF DCCF CSTD2 CSTD1 CSTD0 CSTD2 CSTD1 CSTD0 CSTD2 CSTD1 CSTD0 CSTD2 CSTD1 CSTD0 CSTD2 CSTD1 CSTD0 CDTO CDTO 50 Product specification SAA7111A LOGIC CONTROL LEVEL BIT ...
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... C-bus bits VCTR1 and VCTR0 (see Fig.9). HDEL1 OFTS1 Product specification SAA7111A CONTROL BITS YDEL1 VREF 625 LINES 0 286 first last first 24 309 23 337 622 ...
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... Switches directly pin 64 GPSW 1998 May 15 BIT NAME LOGIC LEVEL COLO 0 COLO 1 VIPB 0 VIPB 1 OEHV 0 OEHV 1 OEYC 0 OEYC 1 COMPO 0 COMPO 1 FECO 0 FECO 1 CM99 0 CM99 1 GPSW 0 GPSW 1 52 Product specification SAA7111A CONTROL BIT ...
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... BIT NAME LOGIC LEVEL AOSL1 0 AOSL0 0 AOSL1 0 AOSL0 1 AOSL1 1 AOSL0 0 AOSL1 1 AOSL0 1 DIT 0 DIT 1 RGB888 0 RGB888 1 CBR 0 CBR 1 TCLO 0 TCLO 1 RTSE0 0 RTSE0 1 RTSE1 0 RTSE1 1 53 Product specification SAA7111A CONTROL BIT ...
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... BCHI1 1 BCHI0 1 CCTR1 0 CCTR0 0 CCTR1 0 CCTR0 1 CCTR1 1 CCTR0 0 CCTR1 1 CCTR0 1 VCTR1 0 VCTR0 0 VCTR1 0 VCTR0 1 VCTR1 1 VCTR0 0 VCTR1 1 VCTR0 1 54 Product specification SAA7111A CONTROL BIT ...
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Acrobat reader. white to force landscape pages to be ... 17.2. UBADDRESS Table 34 Start of decoded data on VPO-port SA 15; ...
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Acrobat reader. white to force landscape pages to be ... 17.2. UBADDRESS VPO- SA 16; ABLE TOP OF DECODED ...
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... LOW = TV time-constant, HIGH = VTR time-constant 1998 May 15 ) ONLY REGISTER FUNCTION ) ONLY REGISTER FUNCTION ) ONLY REGISTER FUNCTION ) ONLY REGISTER FUNCTION 57 Product specification SAA7111A STATUS BIT DATA BITS DATA BITS STATUS BIT ...
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... TUF-block filter curve 6 V handbook, full pagewidth (dB Fig.42 Interpolation filter for the upsampled CVBS-signal. 1998 May Fig.41 Anti-alias filter Product specification SAA7111A MGD138 (MHz) MGG067 (MHz) ...
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... Fig.44 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture factors. 1998 May 15 (1) (2) (4) ( (1) (2) (3) ( Product specification SAA7111A MGD139 (1) (2) (4) ( (MHz) MGD140 (4) (3) (2) ( (MHz) ...
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... V Y (dB (1) = C0H; (2) = C1H; (3) = C2H; (4) = C3H. Fig.46 Luminance control SA 09H, Y/C mode, prefilter on, different aperture factors. 1998 May (1) (2) (3) ( Product specification SAA7111A MGD141 (1) (2) (4) ( (MHz) MGD142 (MHz) ...
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... Fig.48 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture band-pass centre frequencies. 1998 May 15 (1) (2) (3) ( Product specification SAA7111A MGD143 (MHz) MGD144 (1) (2) (4) ( (MHz ...
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... Fig.50 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre frequencies. 1998 May Product specification SAA7111A (4) (3) (2) ( (MHz) (1) (2) (4) ( (MHz) MGD145 8 MGD146 ...
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... CHBW [ 10; (4) CHBW [ 11 C-BUS START SET-UP The given values force the following behaviour of the SAA7111A: – The analog input AI11 expects a signal in CVBS format; analog anti-alias filter active – Automatic field detection – YUV 16-bit output format enabled – ...
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... VSTA7 to VSTA0 VSTO7 to VSTO0 VSTO8, and VSTA8 F2VAL, F2RDY, F1VAL, and F1RDY P1, BYTE1 ( P2, BYTE2 ( STTC, HLCK, FIDT, GLIMT, GLIMB, WIPA, SLTCA and CODE 64 Product specification SAA7111A VALUES (BIN START ...
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... 2.5 scale (1) ( 0.27 0.18 10.1 10.1 12.15 0.5 0.17 0.12 9.9 9.9 11.85 REFERENCES JEDEC EIAJ detail 12.15 0.75 1.0 0.2 0.12 0.1 11.85 0.45 EUROPEAN PROJECTION Product specification SAA7111A SOT314 (1) ( 1.45 1. 1.05 1.05 0 ISSUE DATE 95-12-19 97-08-01 ...
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... scale (1) ( 0.45 0.23 14.1 14.1 17.45 0.8 0.30 0.13 13.9 13.9 16.95 REFERENCES JEDEC EIAJ MS-022 detail 17.45 1.03 1.60 0.16 0.16 0.10 16.95 0.73 EUROPEAN PROJECTION Product specification SAA7111A SOT393 (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 96-05-21 97-08-04 ...
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... Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 67 Product specification SAA7111A ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1998 May 15 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 68 Product specification SAA7111A 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Enhanced Video Input Processor (EVIP) 1998 May 15 NOTES 69 Product specification SAA7111A ...
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... Philips Semiconductors Enhanced Video Input Processor (EVIP) 1998 May 15 NOTES 70 Product specification SAA7111A ...
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... Philips Semiconductors Enhanced Video Input Processor (EVIP) 1998 May 15 NOTES 71 Product specification SAA7111A ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, ...