MC9S12DG128CFU Motorola, MC9S12DG128CFU Datasheet
MC9S12DG128CFU
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MC9S12DG128CFU Summary of contents
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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized ...
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MC9S12DT128 Device User Guide — V02.09 Revision History Version Revision Effective Number Date Date 18 Jun 18 June V01.00 2001 2001 23 July 23 July V01.01 2001 2001 23 Sep 23 Sep V01.02 2001 2001 12 Oct 12 Oct V01.03 ...
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Version Revision Effective Number Date Date 08 Mar 08 Mar V02.02 2002 2002 14 Mar 14 Mar V02.03 2002 2002 16 Aug 16 Aug V02.04 2002 2002 12 Sep 12 Sep V02.05 2002 2002 06 Nov 06 Nov V02.06 2002 ...
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MC9S12DT128 Device User Guide — V02.09 Version Revision Effective Number Date Date 29 Jan 29 Jan V02.07 2003 2003 26 Feb 26 Feb V02.08 2003 2003 15 Oct 15 Oct V02.09 2003 2003 4 Author Description of Changes Added 3L40K ...
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MC9S12DT128 Device User Guide — V02.09 5 ...
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MC9S12DT128 Device User Guide — V02.09 6 ...
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Table of Contents Section 1 Introduction ...
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MC9S12DT128 Device User Guide — V02.09 2.3.21 PH6 / KWH6 — Port H I/O Pin ...
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PT[7:0] / IOC[7:0] — Port T I/O Pins [7: ...
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MC9S12DT128 Device User Guide — V02.09 6.1.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Section 20 MSCAN Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Section 21 Port ...
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MC9S12DT128 Device User Guide — V02.09 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 0-1 Order Partnumber Example ...
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MC9S12DT128 Device User Guide — V02.09 14 ...
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... EEPROM Control Register (eets2k) ........................................................44 $011C - $011F Reserved for RAM Control Register ........................................................45 $0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................45 $0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ..............................................46 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout .47 MC9S12DT128 Device User Guide — V02.09 ...
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... MC9S12DT128 Device User Guide — V02.09 $0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) ..............................................48 $01C0 - $01FF Reserved ..................................................................................................49 $0200 - $023F Reserved ..................................................................................................49 $0240 - $027F PIM (Port Integration Module) ..................................................................50 $0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ..............................................52 $02C0 - $02FF Reserved ..................................................................................................53 $0300 - $035F Byteflight ..................................................................................................53 $0360 - $03FF Reserved ..................................................................................................55 Table 1-3 Assigned Part ID Numbers ...
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Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 MC9S12DT128 Device ...
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MC9S12DT128 Device User Guide — V02.09 18 ...
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Derivative Differences and Document References Derivative Differences Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. MC9S12DT128E, Modules MC9S12DT128 # of CANs 3 ...
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MC9S12DT128 Device User Guide — V02.09 • Registers – Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a derivative without CAN0 (see Table 0-1). – Do not write or read CAN1 registers ...
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The Byteflight pin functionality (BF_PSLM, BF_PERR, BF_PROK, BF_PSYN, TX_BF, RX_BF) is not available on port PM7, PM6, PM5, PM4, PM3 and PM2, if using a derivative without Byteflight (see Table 0-1). – Do not write MODRR1 and MODRR0 Bit ...
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MC9S12DT128 Device User Guide — V02.09 – Port K Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at Base+$000C. Therefore care must be taken not to clear this ...
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... User Guide Motorola Scalable CAN (MSCAN) Block User Guide Voltage Regulator (VREG) Block User Guide Port Integration Module (PIM_9DTB128) Block User Guide Byteflight (BF) Block User Guide MC9S12DT128 Device User Guide — V02.09 Version Document Order Number V02 S12MSCANV2/D V01 S12VREGV1/D V02 ...
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MC9S12DT128 Device User Guide — V02.09 24 ...
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Section 1 Introduction 1.1 Overview The MC9S12DT128 microcontroller unit (MCU 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, ...
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MC9S12DT128 Device User Guide — V02.09 – Digital filtering – Programmable rising or falling edge trigger • Memory – 128K Flash EEPROM – 2K byte EEPROM – 8K byte RAM • Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External ...
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... Emulation Expanded Narrow Mode • Special Operating Modes – Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Motorola use only) – Special Peripheral Mode (Motorola use only) Low power modes • Stop Mode • Pseudo Stop Mode • ...
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MC9S12DT128 Device User Guide — V02.09 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DT128 device. 28 ...
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Figure 1-1 MC9S12DT128 Block Diagram 128K Byte Flash EEPROM 8K Byte RAM 2K Byte EEPROM VDDR VSSR Voltage Regulator VREGEN VDD1,2 VSS1,2 Single-wire Background BKGD CPU Debug Module XFC Clock and VDDPLL Reset PLL Periodic Interrupt VSSPLL Generation COP Watchdog ...
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... Motorola Scalable CAN (CAN1) $01C0 – $01FF Reserved $0200 – $023F Reserved $0240 – $027F Port Integration Module (PIM) $0280 – $02BF Motorola Scalable CAN (CAN4) $02C0 – $02FF Reserved $0300 – $035F Byteflight (BF) $0360 – $03FF Reserved $0000 – ...
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Table 1-1 Device Memory Map Address Fixed Flash EEPROM array incl. 0.5K, 1K Protected Sector at end $C000 – $FFFF and 256 bytes of Vector Space at $FF80 Figure 1-2 MC9S12DT128 Memory Map $0000 $0400 $0800 $1000 ...
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MC9S12DT128 Device User Guide — V02.09 1.5.1 Detailed Register Map $0000 - $000F Address Name Read: $0000 PORTA Write: Read: $0001 PORTB Write: Read: $0002 DDRA Write: Read: $0003 DDRB Write: Read: $0004 Reserved Write: Read: $0005 Reserved Write: Read: ...
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INT map (HCS12 Interrupt) Address Name Bit 7 Read: $0015 ITCR Write: Read: $0016 ITEST INTE Write: $0017 - $0017 MMC map (HCS12 Module Mapping Control) Address Name Bit 7 Read: ...
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MC9S12DT128 Device User Guide — V02.09 $0020 - $0027 Address Name Read: $0020 - Reserved $0027 Write: $0028 - $002F Address Name Read: $0028 BKPCT0 Write: Read: $0029 BKPCT1 Write: Read: $002A BKP0X Write: Read: $002B BKP0H Write: Read: $002C ...
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CRG (Clock and Reset Generator) Address Name Bit 7 Read: $0034 SYNR Write: Read: $0035 REFDV Write: Read: CTFLG $0036 TEST ONLY Write: Read: $0037 CRGFLG RTIF Write: Read: $0038 CRGINT RTIE Write: Read: $0039 CLKSEL PLLSEL ...
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MC9S12DT128 Device User Guide — V02.09 $0040 - $007F Address Name Read: $004A TCTL3 Write: Read: $004B TCTL4 Write: Read: $004C TIE Write: Read: $004D TSCR2 Write: Read: $004E TFLG1 Write: Read: $004F TFLG2 Write: Read: $0050 TC0 (hi) Write: ...
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ECT (Enhanced Capture Timer 16 Bit 8 Channels) Address Name Bit 7 Read: $0063 PACN2 (lo) Bit 7 Write: Read: $0064 PACN1 (hi) Bit 7 Write: Read: $0065 PACN0 (lo) Bit 7 Write: Read: $0066 MCCTL MCZI ...
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MC9S12DT128 Device User Guide — V02.09 $0040 - $007F Address Name Read: $007C TC2H (hi) Write: Read: $007D TC2H (lo) Write: Read: $007E TC3H (hi) Write: Read: $007F TC3H (lo) Write: $0080 - $009F Address Name Read: $0080 ATD0CTL0 Write: ...
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ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Read: Bit15 $0092 ATD0DR1H Write: Read: Bit7 $0093 ATD0DR1L Write: Read: Bit15 $0094 ATD0DR2H Write: Read: Bit7 $0095 ATD0DR2L Write: Read: Bit15 $0096 ATD0DR3H ...
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MC9S12DT128 Device User Guide — V02.09 $00A0 - $00C7 Address Name Read: $00A9 PWMSCLB Write: Read: PWMSCNTA $00AA Test Only Write: PWMSCNTB Read: $00AB Test Only Write: Read: $00AC PWMCNT0 Write: Read: $00AD PWMCNT1 Write: Read: $00AE PWMCNT2 Write: Read: ...
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PWM (Pulse Width Modulator 8 Bit 8 Channel) Address Name Bit 7 Read: $00C2 PWMDTY6 Bit 7 Write: Read: $00C3 PWMDTY7 Bit 7 Write: Read: $00C4 PWMSDN PWMIF Write: Read: $00C5 Reserved Write: Read: $00C6 Reserved Write: ...
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MC9S12DT128 Device User Guide — V02.09 $00D0 - $00D7 Address Name Read: $00D5 SCI1SR2 Write: Read: $00D6 SCI1DRH Write: Read: $00D7 SCI1DRL Write: $00D8 - $00DF Address Name Read: $00D8 SPI0CR1 Write: Read: $00D9 SPI0CR2 Write: Read: $00DA SPI0BR Write: ...
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BDLC (Byte Level Data Link Controller J1850) Address Name Bit 7 Read: $00E8 DLCBCR1 IMSG Write: Read: $00E9 DLCBSVR Write: Read: $00EA DLCBCR2 SMRST Write: Read: $00EB DLCBDR D7 Write: Read: $00EC DLCBARD Write: Read: $00ED DLCBRSR ...
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MC9S12DT128 Device User Guide — V02.09 $0100 - $010F Address Name Read: FDIVLD $0100 FCLKDIV Write: Read: KEYEN1 KEYEN0 $0101 FSEC Write: Read: $0102 FTSTMOD Write: Read: $0103 FCNFG Write: Read: $0104 FPROT Write: Read: $0105 FSTAT Write: Read: $0106 ...
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EEPROM Control Register (eets2k) Address Name Bit 7 Read: $0119 EADDRLO Bit 7 Write: Read: $011A EDATAHI Bit 15 Write: Read: $011B EDATALO Bit 7 Write: $011C - $011F Reserved for RAM Control Register Address Name Bit ...
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... Bit15 Bit7 Bit6 0 0 Bit15 Bit7 Bit6 0 0 CAN0 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 RXACT SYNCH RXFRM CSWAI CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 RSTAT1 ...
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... CAN0 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Read: $0146 CAN0TFLG Write: Read: $0147 CAN0TIER Write: Read: $0148 CAN0TARQ Write: Read: $0149 CAN0TAAK Write: Read: $014A CAN0TBSEL Write: Read: $014B CAN0IDAC Write: Read: $014C Reserved Write: Read: $014D Reserved ...
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... ID3 DB7 DB6 DB5 DB4 PRIO7 PRIO6 PRIO5 PRIO4 TSR15 TSR14 TSR13 TSR12 TSR7 TSR6 TSR5 TSR4 CAN1 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 RXACT SYNCH RXFRM CSWAI CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 ...
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... CAN1 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Read: $0185 CAN1RIER WUPIE Write: Read: $0186 CAN1TFLG Write: Read: $0187 CAN1TIER Write: Read: $0188 CAN1TARQ Write: Read: $0189 CAN1TAAK Write: Read: $018A CAN1TBSEL Write: Read: $018B CAN1IDAC Write: Read: $018C ...
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MC9S12DT128 Device User Guide — V02.09 $0240 - $027F Address Name Read: $0240 PTT Write: Read: $0241 PTIT Write: Read: $0242 DDRT Write: Read: $0243 RDRT Write: Read: $0244 PERT Write: Read: $0245 PPST Write: Read: $0246 Reserved Write: Read: ...
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PIM (Port Integration Module) Address Name Bit 7 Read: PTIP7 $0259 PTIP Write: Read: $025A DDRP DDRP7 Write: Read: $025B RDRP RDRP7 Write: Read: $025C PERP PERP7 Write: Read: $025D PPSP PPSP7 Write: Read: $025E PIEP PIEP7 ...
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... Write: $029C - CAN0IDMR4 - Read: $029F CAN0IDMR7 Read: $02A0 - CAN4RXFG $02AF Write: Read: $02B0 - CAN4TXFG $02BF Write: 52 CAN4 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 RXACT SYNCH RXFRM CSWAI CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 ...
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Reserved Address Name Bit 7 Read: $02C0 - Reserved $02FF Write: $0300 - $035F Byteflight Address Name Bit 7 Read: $0300 BFMCR INITRQ MASTER ALARM Write: Read: $0301 BFFSIZR Write: Read: $0302 BFTCR1 TWX0T7 TWX0T6 TWX0T5 TWX0T4 ...
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MC9S12DT128 Device User Guide — V02.09 $0300 - $035F Address Name Read: $0315 BFFIDRMR Write: Read: $0316 Reserved Write: Read: $0317 Reserved Write: Read: $0318 Reserved Write: Read: $0319 Reserved Write: Read: $031A Reserved Write: Read: $031B Reserved Write: Read: ...
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Address Name Read: $0360 - Reserved $03FF Write: 1.6 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ...
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MC9S12DT128 Device User Guide — V02.09 56 ...
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Section 2 Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals built from the signal description sections of the Block User Guides of ...
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MC9S12DT128 Device User Guide — V02.09 SS1/PWM3/KWP3/PP3 1 SCK1/PWM2/KWP2/PP2 2 MOSI1/PWM1/KWP1/PP1 3 MISO1/PWM0/KWP0/PP0 4 XADDR17/PK3 5 XADDR16/PK2 6 XADDR15/PK1 7 XADDR14/PK0 8 IOC0/PT0 9 IOC1/PT1 10 IOC2/PT2 11 IOC3/PT3 12 VDD1 13 VSS1 14 IOC4/PT4 15 IOC5/PT5 16 IOC6/PT6 17 ...
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SS1/PWM3/KWP3/PP3 1 SCK1/PWM2/KWP2/PP2 2 MOSI1/PWM1/KWP1/PP1 3 MISO1/PWM0/KWP0/PP0 4 IOC0/PT0 5 IOC1/PT1 6 IOC2/PT2 7 IOC3/PT3 8 VDD1 9 VSS1 10 MC9S12DG128E, MC9S12DG128, IOC4/PT4 11 IOC5/PT5 12 IOC6/PT6 13 IOC7/PT7 14 MODC/TAGHI/BKGD 15 ADDR0/DATA0/PB0 16 ADDR1/DATA1/PB1 17 ADDR2/DATA2/PB2 18 ADDR3/DATA3/PB3 19 ...
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MC9S12DT128 Device User Guide — V02.09 SS1/PWM3/KWP3/PP3 1 SCK1/PWM2/KWP2/PP2 2 MOSI1/PWM1/KWP1/PP1 3 MISO1/PWM0/KWP0/PP0 4 IOC0/PT0 5 IOC1/PT1 6 IOC2/PT2 7 IOC3/PT3 8 VDD1 9 VSS1 10 IOC4/PT4 11 IOC5/PT5 12 IOC6/PT6 13 IOC7/PT7 14 MODC/TAGHI/BKGD 15 ADDR0/DATA0/PB0 16 ADDR1/DATA1/PB1 17 ...
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Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 RESET — — TEST — — VREGEN — — XFC — — BKGD TAGHI MODC PAD[15] AN1[7] ETRIG1 PAD[14:8] AN1[6:0] — PAD[7] AN0[7] ETRIG0 PAD[6:0] AN0[6:0] — ADDR[15:8]/ ...
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MC9S12DT128 Device User Guide — V02.09 Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 PH4 KWH4 --- PH3 KWH3 SS1 PH2 KWH2 SCK1 PH1 KWH1 MOSI1 PH0 KWH0 MISO1 PJ7 KWJ7 TXCAN4 PJ6 KWJ6 RXCAN4 PJ[1:0] ...
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Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 PP7 KWP7 PWM7 PP6 KWP6 PWM6 PP5 KWP5 PWM5 PP4 KWP4 PWM4 PP3 KWP3 PWM3 PP2 KWP2 PWM2 PP1 KWP1 PWM1 PP0 KWP0 PWM0 PS7 SS0 — PS6 ...
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... The TEST pin must be tied to VSS in all applications. 2.3.4 XFC — PLL Loop Filter Pin PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. Figure 2-4 PLL Loop Filter Connections 2.3.5 BKGD / TAGHI / MODC — ...
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PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15] PAD15 is a general purpose input pin and analog input of the analog to digital converter ATD1. It can act as an external trigger input for the ATD1. ...
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MC9S12DT128 Device User Guide — V02.09 MCU * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor ...
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PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin used as a MCU operating mode select pin during reset. The state of this pin is latched ...
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... PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller (CAN0, CAN4) or the serial clock pin SCL of the IIC module. ...
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... PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller (CAN0, CAN4) or the serial data pin SDA of the IIC module. ...
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... PM4 is a general purpose input or output pin. It can be configured as the correct synchronisation pulse reception/transmission output pulse pin of Byteflight. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers (CAN0 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0). 2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — ...
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PP5 / KWP5 / PWM5 — Port P I/O Pin 5 PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can ...
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MC9S12DT128 Device User Guide — V02.09 2.3.51 PS5 / MOSI0 — Port S I/O Pin 5 PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during ...
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Pin Number Mnemonic 112-pin QFP VDDR 41 VSSR 40 VDDX 107 VSSX 106 VDDA 83 VSSA 86 VRL 85 VRH 84 VDDPLL 43 VSSPLL 45 VREGEN 97 NOTE: All VSS pins must be connected together in the application. 2.4.1 VDDX,VSSX ...
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MC9S12DT128 Device User Guide — V02.09 2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter. It also provides ...
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Section 3 System Clock Description 3.1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block ...
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MC9S12DT128 Device User Guide — V02.09 76 ...
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Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12DT128. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for ...
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MC9S12DT128 Device User Guide — V02.09 Table 4-3 Voltage Regulator VREGEN VREGEN 1 0 4.3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: • Protection of ...
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Unsecuring the Microcontroller In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode or via a .sequence of BDM commands. Unsecuring is also possible ...
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Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the CPU Reference Manual for information on resets and interrupts. 5.2 Vectors 5.2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of priority. ...
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MC9S12DT128 Device User Guide — V02.09 $FFCA, $FFCB Modulus Down Counter underflow $FFC8, $FFC9 Pulse Accumulator B Overflow $FFC6, $FFC7 CRG PLL lock $FFC4, $FFC5 CRG Self Clock Mode $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, ...
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NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins. 5.3.2 Memory Refer to Table ...
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Section 6 HCS12 Core Block Description 6.1 CPU Block Description Consult the CPU Reference Manual for information on the CPU. 6.1.1 Device-specific information When the CPU Reference Manual refers to cycles this is equivalent to Bus Clock periods ...
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MC9S12DT128 Device User Guide — V02.09 6.4 HCS12 Interrupt (INT) Block Description Consult the INT Block Guide for information on the HCS12 Interrupt module. 6.5 HCS12 Background Debug Module (BDM) Block Description Consult the BDM Block Guide for information on ...
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Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer module.When the ECT_16B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode. Section 10 Analog to Digital Converter (ATD) Block Description There ...
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... Section 19 RAM Block Description This module supports single-cycle misaligned word accesses without wait states. Section 20 MSCAN Block Description There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12DT128. Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module. 88 ...
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Section 21 Port Integration Module (PIM) Block Description Consult the PIM_9DTB128 Block User Guide for information about the Port Integration Module. Section 22 Voltage Regulator (VREG) Block Description Consult the VREG Block User Guide for information about the dual output ...
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MC9S12DT128 Device User Guide — V02.09 • Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. • VSSPLL must be directly connected to VSSR. • Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied ...
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Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator VSSX VDD1 C1 VSS1 VSSR VDDR MC9S12DT128 Device User Guide — V02.09 VSSA C3 Q1 VSSPLL VDDPLL R1 VDDA VSS2 C2 VDD2 91 ...
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MC9S12DT128 Device User Guide — V02.09 Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, and MC9S12DJ128) Colpitts Oscillator VDD1 C1 VSS1 92 VSSA VSSX VSSR VDDR Q1 VSSPLL VDDPLL R1 C3 VDDA VSS2 C2 VDD2 ...
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Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VSSX VDD1 C1 VSS1 VSSR VDDR VDDPLL MC9S12DT128 Device User Guide — V02.09 VSSA C3 VSSPLL VDDA VSS2 C2 VDD2 93 ...
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MC9S12DT128 Device User Guide — V02.09 Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, and MC9S12DJ128) Pierce Oscillator VDD1 C1 VSS1 94 VSSA VSSX VSSR R3 VDDR R2 Q1 VSSPLL VDDPLL R1 C3 VDDA VSS2 C2 VDD2 VSSPLL ...
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Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128) Pierce Oscillator VDD1 C1 VSS1 VSSR VDDR MC9S12DT128 Device User Guide — V02.09 C3 VSSA VSSX VSSPLL VSSPLL VDDPLL R1 VDDA VSS2 C2 VDD2 95 ...
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MC9S12DT128 Device User Guide — V02.09 96 ...
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Appendix A Electrical Characteristics A.1 General This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To ...
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MC9S12DT128 Device User Guide — V02.09 NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing ...
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A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains ...
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MC9S12DT128 Device User Guide — V02.09 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device ...
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Section A.1.8 Power Dissipation and Thermal Characteristics. Rating I/O, Regulator and Analog Supply Voltage 1 Digital Logic Supply Voltage 1 PLL Supply Voltage Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA ...
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MC9S12DT128 Device User Guide — V02. Ambient Temperature Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ C/W] JA The total power dissipation can be calculated from: P INT = Chip ...
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Table A-5 Thermal Package Characteristics Num C Rating 1 T Thermal Resistance LQFP112, single sided PCB Thermal Resistance LQFP112, double sided PCB with 2 internal planes 3 T Junction to Board LQFP112 4 T Junction to Case ...
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MC9S12DT128 Device User Guide — V02.09 Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 C Input Hysteresis ...
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A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed ...
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MC9S12DT128 Device User Guide — V02.09 NOTES: 1. PLL off, Oscillator in Colpitts Mode 2. At those low power dissipation levels T 106 = T can be assumed J A ...
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A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results ...
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MC9S12DT128 Device User Guide — V02.09 specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of ...
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A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted ...
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MC9S12DT128 Device User Guide — V02.09 DNL LSB V i-1 $3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Figure ...
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A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. ...
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MC9S12DT128 Device User Guide — V02.09 The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to ...
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A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating ...
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A.4 Voltage Regulator The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL ...
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A.5 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.5.1 Startup Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can ...
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MC9S12DT128 Device User Guide — V02.09 A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal ...
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A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the ...
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MC9S12DT128 Device User Guide — V02.09 The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, C typical values are 50. = 0.9 ensures a good transient response. f < ...
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The relative deviation its maximum for one clock period, and decreases towards zero for larger nom number of clock periods (N). Defining the jitter as For ...
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MC9S12DT128 Device User Guide — V02.09 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Conditions are shown in Table A-4 unless otherwise ...
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A.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P MSCAN Wake-up dominant pulse filtered 2 P MSCAN Wake-up dominant pulse pass MC9S12DT128 Device User Guide — V02.09 ...
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A.7 SPI A.7.1 Master Mode Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-18 (OUTPUT) 2 SCK (CPOL 0) (OUTPUT) 4 SCK (CPOL 1) (OUTPUT MISO 2 MSB ...
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MC9S12DT128 Device User Guide — V02. (OUTPUT SCK (CPOL 0) (OUTPUT) 4 SCK (CPOL 1) (OUTPUT) 5 MISO MSB IN (INPUT) 9 MOSI PORT DATA MASTER MSB OUT (OUTPUT) 1.If configured as output 2. LSBF = ...
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A.7.2 Slave Mode Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-19. SS (INPUT) SCK (CPOL 0) (INPUT) 2 SCK (CPOL 1) (INPUT) 7 MISO MSB OUT SLAVE (OUTPUT MOSI ...
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MC9S12DT128 Device User Guide — V02.09 Table A-19 SPI Slave Mode Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs Num C Rating 1 P Operating Frequency P SCK Period t = ...
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A.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-20. All major bus signals are included in the diagram. While both a data write ...
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MC9S12DT128 Device User Guide — V02.09 ECLK PE4 5 9 Addr/Data data (read) PA, PB Addr/Data data (write) PA Non-Multiplexed Addresses PK5:0 ECS PK7 24 R/W PE2 27 LSTRB PE3 30 NOACC PE7 33 PIPO0 PIPO1, PE6,5 Figure ...
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Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 1 P Frequency of operation (E-clock Cycle time 3 D Pulse width, E low Pulse width, ...
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MC9S12DT128 Device User Guide — V02.09 Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 32 D NOACC hold time 33 D IPIPO[1:0] delay time D IPIPO[1:0] valid time to ...
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Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12DT128 packages. MC9S12DT128 Device User Guide — V02.09 133 ...
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MC9S12DT128 Device User Guide — V02.09 B.2 112-pin LQFP package 0. PIN 1 112 IDENT 1 VIEW 0.050 C1 VIEW AB Figure 23-6 112-pin LQFP mechanical ...
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B.3 80-pin QFP package 0.20 M 0.05 A-B 0. -C- H SEATING PLANE G DATUM -H- PLANE W X DETAIL C Figure 1 80-pin QFP Mechanical Dimensions (case no. 841B) MC9S12DT128 ...
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User Guide End Sheet MC9S12DT128 Device User Guide — V02.09 137 ...
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MC9S12DT128 Device User Guide — V02.09 138 FINAL PAGE OF 138 PAGES ...