M2V64S40BTP-10 Mitsumi Electronics, Corp., M2V64S40BTP-10 Datasheet
M2V64S40BTP-10
Related parts for M2V64S40BTP-10
M2V64S40BTP-10 Summary of contents
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... PRELIMINARY DESCRIPTION M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2V64S20BTP,M2V64S30BTP,M2V64S40BTP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems ...
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... DQ0-3(x4), DQ0-7(x8), DQ0-15(x16) DQM (x4, x8) ,DQML/U (x16) A0-11 BA0,1 Vdd VddQ Vss VssQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) M2V64S20BTP M2V64S30BTP M2V64S40BTP Vdd 1 54 DQ0 2 53 VddQ 3 52 DQ1 ...
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... Type Designation Code This rule is applied only to Synchronous DRAM families beyond 64M B-version 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) DQ0-3 (x4) DQ0-7 (x8) DQ0-15 (x16) I/O Buffer Memory Array Memory Array ...
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... Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh ...
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... REFA command starts auto-refresh cycle. Refresh address including bank address are generated inter-nally. After this command, the banks are precharged automatically. 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Chip Select : L=select, H=deselect Command Command define basic commands ...
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... Burst Terminate TBST Mode Register Set MRS H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) CKE CKE /CS /RAS /CAS n ...
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... READ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) /WE Address Command DESEL NOP TBST L X BA, CA, A10 READ / WRITE ILLEGAL BA, RA ...
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... 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) /WE Address Command X X DESEL H X NOP L BA TBST L H BA, CA, A10 READ / READA WRITE / L L BA, CA, A10 ...
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... WRITE RE- COVERING 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) /WE Address Command DESEL NOP TBST L X BA, CA, A10 READ / WRITE ILLEGAL BA, RA ...
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... NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) /CAS /WE Address Command X ...
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... EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) /CS /RAS /CAS /WE Add X ...
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... CKEH WRITEA CKEL WRITEA SUSPEND CKEH POWER POWER APPLIED ON 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) REFS MRS REFA IDLE CLK CKEH ACT CKEL CKEH TBST (for Full Page) ROW ACTIVE WRITE ...
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... LATENCY MODE WRITE 0 BURST MODE SINGLE BIT 1 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT LTMODE BURST 3 LENGTH R R ...
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... Terminate) command should be issued to stop the output of data. Burst Length Timing( CL=2 ) tRCD CLK Command ACT READ X Y Address 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) READ tRCD ...
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... Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT /CAS Latency Burst Length Column Addressing Sequential ...
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... The internal precharge starts at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) tRCmin ACT READ PRE ...
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... A10 Xa A11 Xa 00 BA0,1 DQ READ Auto-Precharge Timing (BL=4) CLK Command ACT CL=3 DQ CL=2 DQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) READ ACT READ Qa0 Qa1 /CAS latency Burst Length BL + tRP READ BL ...
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... DQ CLK Command ACT tRCD A0-9 Xa A10 Xa A11 Xa BA0 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Multi Bank Interleaving WRITE (BL=4) Write ACT Write tRCD Da0 Da1 Da2 ...
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... CLK Command ACT X Address DQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT ...
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... Read Interrupted by Write (BL=4, CL=3) CLK Command READ A0-9 Yi A10 0 A11 BA0,1 00 DQM(x4,x8) DQMU/L(x16 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) READ READ Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Write Qai0 Daj0 ...
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... The figure below shows examples of BL=4. CLK Command DQ Command CL=3 DQ Command DQ Command DQ Command CL=2 DQ Command DQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Read Interrupted by Precharge (BL=4) READ PRE Q0 READ PRE Q0 READ PRE Q0 READ PRE Q0 Q1 READ PRE Q0 Q1 READ PRE ...
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... TBST. Read Interrupted by Burst Terminate(BL=4) CLK Command DQ Command CL=3 DQ Command DQ Command DQ CL=2 Command DQ Command DQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) READ TBST READ TBST READ TBST Q0 READ TBST READ ...
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... Yi Yj A10 0 0 A11 BA0 DQM(x4,x8) DQMU/L(x16) Dai0 DQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Write Interrupted by Write (BL=4) Write Write Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Write ...
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... CLK WRITE Command Yi A0-9 0 A10 BA 0 DQM(x4,x8) DQMU/L(x16) Dai0 DQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Write Interrupted by Precharge (BL=4) PRE ACT tWR tRP Dai2 TBST Dai1 Dai2 MITSUBISHI ELECTRIC ...
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... REFA command. CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1 Auto Refresh on All Banks 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Auto-Refresh NOP or DESELECT minimum tRC MITSUBISHI ELECTRIC 25 MITSUBISHI LSIs Auto Refresh on All Banks ...
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... CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1 Self Refresh Entry 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Self-Refresh Stable CLK Self Refresh Exit MITSUBISHI ELECTRIC 26 MITSUBISHI LSIs NOP tSRX new command X 00 minimum tRC ...
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... CLK CKE Write Command 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Power Down by CKE Standby Power Down NOP NOP NOP NOP NOP Active Power Down NOP NOP NOP NOP NOP DQ Suspend by CKE ...
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... CLK Command Write DQML DQMU DQ0-7 D0 DQ8- masked by DQML=H 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) DQM Function READ D2 D3 DQM Function READ MITSUBISHI ELECTRIC 28 MITSUBISHI LSIs Q0 ...
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... Input Capacitance, contorl pin CI(C) CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ta = 25ºC Min. 3 ...
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... VOL (DC) Low-level Output Voltage (DC) Off-state Output Current IOZ Input Current I I 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Organi- Symbol zation single bank operation Icc1 tCLK = 15ns Icc2N x4/x8/x16 CKE = VIHmin CLK = VILmax ...
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... Mode Register Set Cycle time Self-refresh Exit time tSRX tPDE Power Down Exit time tREF Refresh Interval time CLK DQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) 0.8V – 2.0V 1.4V Limits -6 Parameter Min. Max. CL=3 7.5 10 CL=2 2.5 2 ...
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... NOTE clock rising time is longer than 1ns, (tr /2–0.5ns) should be added to the parameter. Output Load Condition V OUT Ext.CL=50pF CLK DQ 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) Limits -6 Min. Max. CL=3 5.4 CL=2 6.0 CL=3 2.7 CL=2 3 ...
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... BA0 ACT#0 WRITE (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT tRC tRP tWR ...
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... BA0 ACT#0 WRITE#0 ACT (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT tRC tRAS tRP tWR tWR ...
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... BA0,1 DQ ACT#0 READ#0 READ to PRE ³BL allows full data out * A9 (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT tRC ...
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... BA0,1 DQ ACT#0 READ#0 ACT (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT tRC tRAS tRP DQM read latency =2 ...
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... BA0 ACT#0 WRITE#0 with ACT#1 AutoPrecharge * A9 (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT tRC BL-1+ tWR + tRP BL-1+ tWR + tRP ...
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... BA0,1 DQ ACT#0 READ#0 with ACT#1 Auto-Precharge * A9 (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT tRC BL+tRP BL+tRP DQM read latency =2 ...
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... BA0 ACT#0 WRITE#0 ACT (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT ...
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... BA0,1 DQ ACT#0 READ#0 ACT (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT DQM read latency CL=3 CL=3 Q0 ...
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... ACT#0 WRITE#0 ACT#1 Burst Write can be interrupted by Write or Read of any active bank (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT ...
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... ACT#0 READ#0 ACT#1 Burst Read can be interrupted by Read or Write of any active bank (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT ...
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... ACT#0 WRITE#0 ACT#1 Burst Write is not interrupted by Precharge of the other bank (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT ...
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... ACT#0 READ#0 ACT#1 Burst Read is not interrupted by Precharge of the other bank (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT ...
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... A 0 BA0,1 DQ Auto-Ref (last of 8 cycles (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT tRSC tRC M 0 Mode ...
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... BA0,1 DQ Auto-Refresh Before Auto-Refresh, all banks must be idle state (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT tRC tRCD ...
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... BA0,1 DQ Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT ...
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... BA0 ACT#0 WRITE (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT masked WRITE#0 ...
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... BA0,1 DQ ACT#0 READ (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT DQM read latency ...
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... DQM(U/ BA0,1 DQ Precharge All * A9 (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT CKE latency ACT#0 ...
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... BA0 ACT#0 WRITE (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT CKE latency ...
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... A9 (x8) and A8,A9 (x16) for column address of read/write are don't care 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) MITSUBISHI ELECTRIC 52 MITSUBISHI LSIs ...