CY7C68013A Cypress Semiconductor Corporation., CY7C68013A Datasheet
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CY7C68013A
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CY7C68013A Summary of contents
Page 1
... Features (CY7C68013A/14A/15A/16A) ■ USB 2.0 USB IF high-speed certified (TID # 40460272) ■ Single chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor ■ Fit, form and function compatible with the FX2 ❐ Pin compatible ❐ Object-code-compatible ❐ Functionally compatible (FX2LP is a superset) ■ ...
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... GPIOs than CY7C68013A/14A enabling additional features in same footprint Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP™ (CY7C68013A/14A low power version of the EZ-USB FX2™ (CY7C68013), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 trans- ceiver, serial interface engine (SIE), enhanced 8051 microcon- troller, and a programmable peripheral interface in a single chip, Document #: 38-08032 Rev ...
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... These signals must be pulled up to 3.3V, even device is connected. 3.4 Buses All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multi- plexed on IO ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 24 MHz × ...
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... USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter onto its stack then jumps to the address 0x0043 where it expects to find a “jump” instruction to the USB Interrupt service routine. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ...
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... Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Notes Table 4 shows the Page ...
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... A powered reset is when the FX2LP powered on and operating and the RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation. For more infor- mation about reset implementation for the FX2 family of products visit http://www.cypress.com. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Notes [3] Page [+] Feedback ...
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... Setup data pointer 2 ■ interface boot load. 3.10.3 External Code Memory The bottom 16 KBytes of program memory is external and therefore the bottom 16 KBytes of internal RAM is accessible only as a data memory. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A RESET Powered Reset Page ...
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... KBytes Code External Memory Data (PSEN#) Memory (RD#,WR#) (Ok to populate (OK to populate data memory program here—RD#/WR# memory here— strobes are not PSEN# strobe active) is not active) Data Code 2 C interface boot access CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback [+] Feedback ...
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... Bytes EP0 IN/OUT E740 E73F 64 Bytes RESERVED E700 E6FF 8051 Addressable Registers (512) E500 E4FF Reserved (128) E480 E47F 128 bytes GPIF Waveforms E400 E3FF Reserved (512) E200 E1FF 512 bytes 8051 xdata RAM E000 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback [+] Feedback ...
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... EP6 512 512 512 1024 1024 512 512 512 EP8 EP8 512 512 512 1024 1024 512 512 512 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EP2 EP2 EP2 EP2 EP2 512 1024 1024 1024 ...
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... FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ...
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... GPIF The GPIF is a flexible 8-bit or 16-bit parallel interface driven by a user programmable finite state machine. It enables the CY7C68013A/15A to perform local bus mastering and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia. The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY) ...
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... Table 9. Part Number Conversion Table EZ-USB FX2 Part Number CY7C68013-56PVC CY7C68013A-56PVXC or CY7C68014A-56PVXC CY7C68013-56PVCT CY7C68013A-56PVXCT or CY7C68014A-56PVXCT 56-pin SSOP – Tape and Reel CY7C68013-56LFC CY7C68013A-56LFXC or CY7C68014A-56LFXC CY7C68013-100AC CY7C68013A-100AXC or CY7C68014A-100AXC CY7C68013-128AC CY7C68013A-128AXC or CY7C68014A-128AXC Note 9. This EEPROM does not have address pins. Document #: 38-08032 Rev. *L ...
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... CY7C68013A/14A and CY7C68015A/16A Differences CY7C68013A is identical to CY7C68014A in form, fit, and functionality. CY7C68015A is identical to CY7C68016A in form, fit, and functionality. CY7C68014A and CY7C68016A have a lower suspend current than CY7C68013A and CY7C68015A respectively and are ideal for power sensitive battery applica- tions. CY7C68015A and CY7C68016A are available in 56-pin QFN package only ...
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... PORTC6/GPIFADR6 PORTC5/GPIFADR5 PORTC4/GPIFADR4 PORTC3/GPIFADR3 PORTC2/GPIFADR2 PORTC1/GPIFADR1 PORTC0/GPIFADR0 PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RxD1OUT PE3/RxD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 6. Signal Port GPIF Master PD7 FD[15] PD6 FD[14] PD5 FD[13] PD4 FD[12] PD3 FD[11] PD2 FD[10] PD1 FD[9] PD0 FD[8] FD[7] PB7 PB6 FD[6] ...
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... Figure 7. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment 1 CLKOUT 2 VCC 3 GND 4 RDY0/*SLRD 5 RDY1/*SLWR RDY2 6 RDY3 7 RDY4 8 RDY5 9 AVCC 10 XTALOUT 11 XTALIN 12 AGND AVCC 18 DPLUS 19 DMINUS 20 AGND 21 A11 A12 22 A13 23 A14 24 A15 25 VCC 26 GND 27 INT4 *IFCLK ...
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... Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment VCC 1 GND 2 RDY0/*SLRD 3 RDY1/*SLWR 4 RDY2 5 RDY3 6 RDY4 7 RDY5 8 AVCC 9 XTALOUT 10 XTALIN 11 AGND AVCC 16 DPLUS 17 DMINUS 18 AGND 19 VCC 20 GND 21 INT4 *IFCLK 26 RESERVED 27 BKPT 28 SCL 29 SDA 30 Document #: 38-08032 Rev. *L ...
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... Figure 9. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment Document #: 38-08032 Rev. *L CY7C68013A/CY7C68014A 56-pin SSOP PD5/FD13 PD4/FD12 PD6/FD14 PD3/FD11 PD7/FD15 PD2/FD10 GND PD1/FD9 CLKOUT PD0/FD8 VCC *WAKEUP GND VCC RDY0/*SLRD ...
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... Figure 10. CY7C68013A/14A/15A/16A 56-pin QFN Pin Assignment RDY0/*SLRD 1 RDY1/*SLWR 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 *IFCLK/**PE0 13 RESERVED 14 Document #: 38-08032 Rev. *L CY7C68013A/CY7C68014A & CY7C68015A/CY7C68016A 56-pin QFN * denotes programmable polarity ** denotes CY7C68015A/CY7C68016A pinout CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ...
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... Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View Document #: 38-08032 Rev CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ...
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... CY7C68013A/15A Pin Descriptions [10] The FX2LP Pin Descriptions follows. Table 11. FX2LP Pin Descriptions 128 100 VF- TQFP TQFP SSOP QFN BGA AVCC AVCC AGND AGND DMINUS DPLUS ...
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... IO/Z I Multiplexed pin whose function is selected by two bits: (PA2) IFCONFIG[1:0]. PA2 is a bidirectional IO port pin. SLOE is an input-only output enable with program- mable polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0]. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback [+] Feedback ...
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... IFCONFIG[1..0]. PB3 is a bidirectional IO port pin. FD[3] is the bidirectional FIFO/GPIF data bus. IO/Z I Multiplexed pin whose function is selected by the (PB4) following bits: IFCONFIG[1..0]. PB4 is a bidirectional IO port pin. FD[4] is the bidirectional FIFO/GPIF data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback [+] Feedback ...
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... Multiplexed pin whose function is selected by the (PD0) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. IO/Z I Multiplexed pin whose function is selected by the (PD1) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback [+] Feedback ...
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... PE3 is a bidirectional IO port pin. RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when sync mode. Otherwise CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...
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... RDY5 is a GPIF input signal. O/Z H Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback [+] Feedback ...
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... TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode. Input N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback [+] Feedback ...
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... N/A Ground. N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description ® chip from suspending interface. Connect to VCC with a 2. peripheral is attached. C-compatible interface. Connect to VCC 2 C-compatible ...
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... PL7 PL6 PL5 PL4 PL3 LINE15 LINE14 LINE13 LINE12 LINE11 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access xxxxxxxx RW reserved reserved reserved 00000000 R CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA2 FLAGA1 ...
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... EP4 0 0 EP8 EP6 EP4 EP8 EP6 EP4 EP2 EP1 EP8 EP6 EP4 EP2 EP1 0 EP0ACK HSGRANT URES SUSP CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access LINE2 LINE1 LINE0 00000000 R COL0 LINE17 LINE16 00000000 R LINE10 LINE9 LINE8 00000000 R LINE2 LINE1 LINE0 ...
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... BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb EP1IN EP0OUT EP0IN 00000000 RW EP1IN EP0OUT EP0IN GPIFWF GPIFDONE 00000000 RW 0 ...
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... TERMA1 TERMA0 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE 0 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access BC2 BC1 BC0 xxxxxxxx RW 0 BUSY STALL 10000000 bbbbbbrb 0 BUSY STALL 00000000 bbbbbbrb ...
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... CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access MSTB2 MSTB1 MSTB0 00100000 RW 0 FALLING RISING 00000001 rrrrrrbb 00000010 RW TC26 TC25 TC24 00000000 RW TC18 TC17 TC16 00000000 RW TC10 ...
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... PS1 PT2 PS0 PT1 DONE D15 D14 D13 D12 D11 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access 0 0 400KHZ xxxxxxxx n/a [14 xxxxxxxx 00000111 00000000 RW A10 A9 A8 00000000 RW ...
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... F0 RS1 RS0 1 ERESI RESI INT6 EX6 EX5 PX6 PX5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access xxxxxxxx xxxxxxxx R RB8_1 TI_1 RI_1 00000000 00000000 RW TR2 CT2 CPRL2 00000000 RW D2 ...
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... Document #: 38-08032 Rev. *L θ θ Junction to Case Case to Ambient Temperature Temperature (°C/W) (°C/W) 24.4 23.3 11.9 34.0 15.5 27.7 10.6 14.6 30.9 27.7 θ θ θ Ca) θ CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A θ Ja Junction to Ambient Temperature θ θ (°C/W) 47.7 45.9 43.2 25.2 58.6 θ θ θ θ Page [+] Feedback [+] Feedback ...
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... Pin Reset after powered on 9.1 USB Transceiver USB 2.0 compliant in full-speed and high-speed modes. 10. AC Electrical Characteristics 10.1 USB Transceiver USB 2.0 compliant in full-speed and high-speed modes. Note 16. Measured at Max VCC, 25°C. Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Conditions 0< V < VCC OUT I = – ...
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... ACC1 CL AV DSU Document #: 38-08032 Rev STBH [18 ACC1 data in Min Typ 20.83 41.66 83 9.6 0 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Max Unit Notes ns 48 MHz ns 24 MHz ns 12 MHz 10 11 Page [+] Feedback [+] Feedback ...
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... Figure 13. Data Memory Read Timing Diagram Stretch = STBH STBL t SCSL t SOEL t [19] DSU ACC1 data in Stretch = 1 [19] t ACC1 Min Typ 20.83 41.66 83.2 9.6 0 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A DSU t DH data in Max Unit Notes ns 48 MHz ns 24 MHz ns 12 MHz 10 11 ...
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... WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is based on the stretch value. Document #: 38-08032 Rev. *L Figure 14. Data Memory Write Timing Diagram t t STBH t data out Stretch = 1 data out Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A AV OFF1 t OFF1 Max Unit Notes 10.7 ns 11.2 ns 11 ...
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... Following is the timing diagram of the read and write strobing function on accessing PORTC. Refer to Section 10.4 for details on propagation delay of RD# and WR# signals. t STBL DATA CAN BE UPDATED BY EXTERNAL LOGIC DATA MUST BE HELD FOR 3 CLK CYLCES t STBL CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Section 10.3 t STBH t STBH Page and [+] Feedback [+] Feedback ...
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... IFCLK must not exceed 48 MHz. Document #: 38-08032 Rev IFCLK t SGA t SRY t RYH valid t t SGD DAH t XCTL N N+1 t XGD Description Min 20.83 8.9 9.2 Description Min. 20.83 2.9 3.7 3.2 4.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [20, 21] Max Unit 7 6.7 ns [21] Max. Unit 200 11 10.7 ...
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... XFLG t Clock to FIFO Data Output Propagation Delay XFD Document #: 38-08032 Rev IFCLK t RDH t SRD t XFLG N N OEon XFD Description Min 20.83 18.7 Description Min. 20.83 12.7 3.7 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t OEoff [21] Max Unit 10.5 ns 10 [21] Max. Unit 200 10 ...
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... OEoff Note 23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08032 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [23] Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Max Unit 10.5 ns 10.5 ns Page [+] Feedback [+] Feedback ...
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... Clock to FLAGS Output Propagation Time XFLG Document #: 38-08032 Rev IFCLK t WRH t SWR SFD FDH t XFLG Description Min 20.83 10.4 9.2 Description Min 20.83 12.1 3.6 3.2 4.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Z [21] Max Unit 9.5 ns [21] Max Unit 200 13.5 ns Page [+] Feedback ...
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... XFLG Document #: 38-08032 Rev WRpwh t WRpwl t t FDH SFD t XFD Description Min t PEH t SPE t XFLG Description Min 20.83 14.6 Description Min 20.83 8.6 2.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [23] Max Unit [20] [21] Max Unit 9.5 ns [21] Max Unit 200 ...
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... SFD FDH FDH SFD FDH SFD X-2 X-1 X-3 t PEpwh t PEpwl t XFLG [23] Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 23 shows this scenario the value [20] t FAH >= t WRH SFD FDH FDH SFD least one IFCLK cycle t SPE t PEH ...
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... Table 30. Slave FIFO Address to Flags/Data Parameters Parameter t FIFOADR[1:0] to FLAGS Output Propagation Delay XFLG t FIFOADR[1:0] to FIFODATA Output Propagation Delay XFD Document #: 38-08032 Rev OEoff t OEon Description Min t XFLG t XFD N N+1 Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Max Unit 10.5 ns 10.5 ns [20] Max Unit 10.7 ns 14.3 ns Page [+] Feedback [+] Feedback ...
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... Parameter t FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time SFA t RD/WR/PKTEND to FIFOADR[1:0] Hold Time FAH Document #: 38-08032 Rev SFA FAH [21] Description Min 20.83 t FAH t SFA [23] Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Max Unit 200 [20] Max Unit Page [+] Feedback [+] Feedback ...
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... FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while (time RDH the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH >= t RDH ...
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... PKTEND pin at least one clock cycle after the rising edge that caused the last byte or word that needs to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to Figure 23 for further details on this timing. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH >= t ...
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... Note In burst read mode, during SLOE is assertion, the data bus driven state and outputs the previous data. After SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incre- mented. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH ...
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... SLWR and the PKTEND signal at the before the SFD same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines have to held constant during the PKTEND assertion. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH t WRpwl ...
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... CY7C68013A-56PVXI CY7C68013A-56LFXC CY7C68013A-56LFXI CY7C68015A-56LFXC CY7C68013A-56BAXC Development Tool Kit CY3684 Reference Design Kit CY4611B Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Package Type RAM Size 128 TQFP – Lead-Free 16K 100 TQFP – Lead-Free 16K 56 SSOP – Lead-Free 16K 56 QFN – Lead-Free 16K 56 VFBGA – ...
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... The FX2LP is available in five packages: ■ 56-pin SSOP ■ 56-pin QFN ■ 100-pin TQFP ■ 128-pin TQFP ■ 56-ball VFBGA Package Diagrams Figure 35. 56-lead Shrunk Small Outline Package O56 (51-85062) Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 51-85062-*C Page [+] Feedback [+] Feedback ...
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... HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.162g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # DESCRIPTION LF56 STANDARD LY56 PB-FREE Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A SIDE VIEW 0.08[0.003] C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 6.1 0°-12° 0.30[0.012] ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1.40±0.05 12°±1° A SEE DETAIL (8X) 0 ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1.40±0.05 12°±1° A SEE DETAIL (8X) 0 ...
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... USB connector. Note 24. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A BOTTOM VIEW Ø0. Ø0. Ø0.30±0.05(56X) ...
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... Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 42. X-ray Image of the Assembly CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 42 Page [+] Feedback [+] Feedback ...
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... Document History Page Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller Document Number: 38-08032 Issue Orig. of REV. ECN NO. Date Change ** 124316 03/17/03 VCS New data sheet *A 128461 09/02/03 VCS Added PN CY7C68015A throughout data sheet Modified Removed word “compatible” where associated with I Corrected grammar and formatting in various locations Updated Sections 3 ...
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... Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller Document Number: 38-08032 Issue Orig. of REV. ECN NO. Date Change *K 420505 See ECN MON Remove SLCS from figure in Section 10.10. Removed indications that SLRD can be asserted simultaneously with SLCS in Section 10 ...